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An ultra-thin ( $20\;\bm{\upmu} {\bf m}$ ), flexible CMOS stress sensor for hybrid systems-in-foil (HySiF) is presented. The system is designed for Fin Ray® grippers in order to measure the emerging stress on the gripper in operation, enabling the extraction of object shape and operation status. In-plane stress is linearly converted to electrical signals proportional to shear stress and normal stress difference using two sensing elements. Each stress signal is processed and digitized by an integrator and a 10-bit SAR ADC. In contrast to rigid chips, the stress cannot be avoided in the sensitive blocks, such as the signal processing chain and digital controller, when an ultra-thin chip is under deformation. The influence of stress levels, up to 350 MPa, is minimized by using stress-insensitive components, design measures, and layout techniques. This work represents the first demonstration of stress-aware top-to-bottom CMOS design on an ultra-thin chip.

In this work an Application Specific Integrated Circuit (ASIC) for an implantable electrochemical biosensor system (SMART implant, Stett et al., 2014) is presented. The ASIC drives the measurement electrodes and performs amperometric measurements for determining the oxygen concentration, potentiometric measurements for evaluating the pH-level as well as temperature measurements. A 10-bit pipeline analog to digital (ADC) is used to digitize the acquired analog samples and is implemented as a single stage to reduce power consumption and chip area. For pH measurements, an offset subtraction technique is employed to raise the resolution to 12-bits. Charge integration is utilized for oxygen and temperature measurements with the capability to cover current ranges between 30 nA and 1 μA. In order to achieve good performance over a wide range of supply and process variations, internal reference voltages are generated from a programmable band-gap regulated circuit and biasing currents are supplied from a wide-range bootstrap current reference. To accommodate the limited available electrical power, all components are designed for low power operation. Also a sequential operation approach is applied, in which essential circuit building blocks are time multiplexed between different measurement types. All measurement sequences and parameters are programmable and can be adjusted for different tissues and media. The chip communicates with external unites through a full duplex two-wire Serial Peripheral Interface (SPI), which receives operational instructions and at the same time outputs the internally stored measurement data. The circuit has been fabricated in a standard 0.5-μm CMOS process and operates on a supply as low as 2.7 V. Measurement results show good performance and agree with circuit simulation. It consumes a maximum of 500 μA DC current and is clocked between 500 kHz and 4 MHz according to the measurement parameters. Measurement results of the on-chip ADC show a Differential Non Linearity (DNL) lower than 0.5 LSB, an Integral Non Linearity (INL) lower than 1 LSB and a Figure of Merit (FOM) of 6 pJ/conversion.

International audience; A variety of diagnostic and therapeutic medical technologies rely on long term implantation of an electronic device to monitor or regulate a patient's condition. One proposed approach to powering these devices is to use a biofuel cell to convert the chemical energy from blood nutrients into electrical current to supply the electronics. We present here an enzymatic microbiofuel cell whose electrodes are directly integrated into a digital electronic circuit. Glucose oxidizing and oxygen reducing enzymes are immobilized on microelectrodes of an application specific integrated circuit (ASIC) using redox hydrogels to produce an enzymatic biofuel cell, capable of harvesting electrical power from just a single droplet of 5 mM glucose solution. Optimisation of the fuel cell voltage and power to match the requirements of the electronics allow self-powered operation of the on-board digital circuitry. This study represents a step towards implantable self-powered electronic devices that gather their energy from physiological fluids.

In the following, RePowerBuf is presented, which is a new concept for filtering and backing electric power to counteract fluctuations from renewables. It can also be used as system-relevant residual power plant in the 100 MW/16.8 GWh range for the transition to renewable energies. It provides for a controlling power range in time scales of one week to 10 ms, operates in all four quadrants of the complex Gaussian plane, filters harmonic components of the line frequency by the mass inertia of its generator and by fuel cells and Li-Ion accumulators as backing systems, augments the short-circuit capacity of the grid, reduces thus its internal resistance, and contributes to its frequency stability. This is accomplished without consuming fuel or polluting the environment by means of closed Power-to-Gas-To-Power Loops.

This paper presents a novel implementation of variable uniaxial mechanical stress model to be used with DC circuit simulation, e.g. using BSIM3v3 transistor model. Based on transistor measurements under various uniaxial stress conditions two stress-dependent parameters are identified, namely the carriers mobility and to a lesser extend the carrier saturation velocity. The effect of the parasitic source/drain resistance on the piezoresistive coefficient determination is addressed in detail. Using the fundamental piezoresistive coefficients, the model has implemented a general relation to calculate the coefficients for arbitrary directions of current and stress in the (0 0 1) silicon (Si) plane. The extended transistor model allows for simulating the effect of uniaxial stress on any MOSFET geometry, under different operation conditions and for any combination of the drain current and stress orientations in the (0 0 1) silicon (Si) plane. The method proposed in this paper is validated by static and dynamic stress-dependent simulations and comparison with experimental data. The method is simulator-independent and can be adapted to other bulk CMOS technologies including SOI processes.

Apart from the ongoing debate about using CMOS active pixel sensors (APS) or CCD imagers for today's consumer and commercial applications the emerging biomedical market presents new opportunities to CMOS APS. Logarithmic response high-dynamic range CMOS (HDRC) cells are the preferred photosensitive circuits for building sensors with contrast and not with illumination dominated outputs. Prominent examples addressing distinct issues in life style and health care are the possibilities to restore vision through a sub-retinal CMOS imager implant and to fabricate a low-cost intracorporeal video probe through a miniature CMOS imager. The sub-retinal imager chip presented here is the first implanted into the eye of a blind human patient with partial restoring of vision.

This work presents a compact wide-range fully integrated sinusoidal signal generator for in vivo Electrochemical Impedance Spectroscopy applications. The circuit is based on a novel architecture combining aspects of direct digital synthesis and interpolation digital to analog conversion. The signal generator demonstrates very precise frequency tuning and high spectral purity, while offering a simple architecture and an uncomplicated clocking scheme. The circuit is fabricated using a 0.5µm sea of transistors CMOS process and occupies 0.32mm2 of active die area. Consuming 110µA at a 3V supply, the circuit covers eight decades of frequency from 1mHz to 100kHz and meets the necessary low energy and high precision requirements for implantable bio-diagnostics.

Hybrid Systems-in-Foil (HySiF) are becoming important for wearable electronics, medical diagnostics and flexible displays, which require mechanical flexibility or adaptivity as well as large area [1]. Ultra-thin chips are an essential part of HySiF as they allow for analog signal processing or complex digital controllers using well established CMOS technology. However, the effect of mechanical stress on the signal processing circuitry (piezoresistivity) has to be considered during the top-to-bottom design in order to realize stress insensitive analog and digital operation. On the other hand, for sensing mechanical stress on the same substrate, the stress effect needs to be maximized [2], thus leading to conflicting design requirements.

A 12-bit counter ramp recycling analog-to-digital converter (ADC) is proposed, which can be configured in a single-step mode for achieving high conversion accuracy as well as in various multi-step modes for yielding high conversion speed. A unique ADC circuit realization is used for the different modes of operation, while a digital control unit is responsible for providing the necessary control signals to the ADC. Similar to common counter ramp architectures, the proposed implementation is suitable for column-parallel readout owing to its simplicity. The proposed variable-step recycling ADC is implemented in a 0.18μm CMOS technology from UMC. Simulation results show good agreement with the expected trade-off between speed and accuracy, which is common to all conventional ADCs.

Many technical products can be milled with a 3-axis CNC equipment and a spherical milling tool. Optical digitizers however have problems in scanning a surface under an angle much larger than 45 °. It is therefore mandatory, especially when digitizing “naturally” looking products, to move an optical digitizer with a 5-axis manipulator into the required viewing positions. We discuss several useful arrangements of axes and digitizer probe, the production of well-ordered, complete and non-ambiguous sets of point coordinates and an intelligent, stochastic compression before exporting to CAD/CAM systems.

A simulation case study to indicate advancement opportunities for a low-voltage complementary organic thin-film transistor (OTFT) technology is presented. A 3-bit unary current-steering digital-to-analog converter (DAC) is used as circuit test vehicle. The study is based on accurate agreement of simulated and measured data, owing to optimized DC/AC SPICE models for both p- and n-type OTFTs. The model is validated by transient measurements of the driving complementary logic thermometer decoder up to a maximum operating frequency of 1 kHz. The case study shows that an improved circuit performance will result from a smaller source and drain overlap with the gate electrode particularly in the n-type OTFT, from avoiding metal interconnect crossings, and from increasing the channel carrier mobility of the n-type OTFT.

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The paper presents a new solution to achieve rail-to-rail common mode input voltage swing for CMOS operational amplifiers. The common mode input range of a MOS differential stage is limited by the threshold voltage of the input transistors. With a pair of complementary input stages the whole range from GND to VDD can be covered. Their drain currents are summed up but the resulting current as well as the DC voltage of the summing node drastically change when one of the input stages turns off near the power rails. The new method applies a built-in feedback loop with an auxiliary opamp for stabilizing the voltage at the summing node. This way a very stable operating point and ideal CMRR can be assured. With selected transistor aspect ratios nearly constant voltage gain can be achieved for the whole common mode input voltage range.

For the adaptive control system of the ASDEX Upgrade tokamak experiment a new digital timing system was developed. Its structure is centralized and distributed. The timing system defines a systemwide 100-ns absolute timescale by central generation of clock and time zero information. Distributed processes are synchronized by time events and state events generated centrally. The timing system supports preprogrammed operation and adaptive operation in close collaboration with the central control computers. A summary is presented of the ASDEX Upgrade timing system design and implementation and of aspects of the integration into the control system. >

This paper gives a short overview of the information technology in today’s car electronics and software components, with main focus on the dramatically increasing intra-car-communication and the accumulative number of electronic control units due to the complexity of current new applications, e.g., the very new semi-autonomous car driving. It is shown how the car industry can learn from parallel computing technologies for succeeding their new upcoming challenges in the close future.

Analog-to-digital conversion requires input amplitudes in the volts range. On the other hand, optical or magnetic sensors deliver sinusoidal signals in the millivolts range and these signals need to be treated digitally. So, two main units will be needed: (1) a programmable gain amplifier and (2) a digital control circuit to maintain certain voltage at the output of the programmable gain amplifier.

The vast and unstoppable rise of virtualization technologies and the related hardware abstraction in the last years established the foundation for new cloud-based infrastructures and new scalable and elastic services. This new paradigm has already found its way in modern data centers and their infrastructures. A positive side effect of these technologies is the transparency of the execution of workloads in a location-independent and hardware-independent manner. For instance, due to higher utilization of underlying hardware thanks to the consolidation of virtual resources or by moving virtual resources to sites with lower energy prices or more available renewable energy resources, data centers can counteract their economic and ecological downsides resulting from their steadily increasing energy demand. This paper introduces a vector-based algorithm for the placement of virtual machines in distributed private cloud environments. After outlining the basic operation of our approach, we provide a formal definition as well as an outlook for further research.

High dynamic range CMOS (HDRCreg) imager technology is reviewed in this paper. Specific aspects of pixel cell layout and circuit/system design, based on which this CMOS imager concept is fully exploited, are highlighted. Various specific applications of HDRCreg are illustrated and future directions are indicated

Carring is a cost-effective, reliable, real-time local area network for cars that is based on a ring topology. Applications of Carring are mechatronic systems in cars, but it is also applicable to general LANs. This paper introduces different medium access methods for Carring. Carring applies synchronous time slots for medium access together with an extension algorithm that allows reallocating unused time slots, thus achieving maximum bandwidth utilization of the ring. Another way of efficient bandwidth allocation in Carring deals with the usage of release algorithms. Furthermore, the fibre distributed data interface (FDDI) is described in order to compare it with Carring.

This paper describes the integration methods applied to incorporate a trigger-timer system into the control system of a tokamak. The described system is a unified means to initiate local actions at each component necessary to create, measure and maintain a plasma. Abstract data representation and model building was used to unify the transmission to the tokamak's components. Lists of a priori scheduled actions as well as online detected events are disseminated by merging them into one stream of high level messages. >

Beyond optimization of position and shape control, producing high performance plasmas relies on precise and coordinated control of plasma parameters. This requires a universal platform, into which control algorithms can flexibly be integrated to adapt to interesting discharge scenarios. With the multitude of processes expected to be implemented, management of real time processes becomes crucial. In this paper the authors shall demonstrate how this issue is raised by the requirement specification of the controller and how it influences its design, implementation and operation.