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The Mars Science Laboratory (MSL) entry capsule has been designed as a lifting entry for sufficient deceleration and precise landing performance. This paper presents the static aerodynamics analysis of the MSL capsule in the hypersonic entry process for exploration mission to Mars. Hypersonic static coefficients were derived from fully three-dimensional computational fluid dynamics solutions with a specified effective specific heat ratio on a typical trajectory state. Aerodynamic performance analysis ascertains the trim characteristics and static stability of the capsule with respect to the center of gravity (CG) location. Analysis results obtained show that CG location determines the trim characteristics and the static stability, and certain CG radial and axial shift alters the lifting entry performance, so that proper aerodynamic configuration and inner equipment layout is needed for CG adjustment to satisfy the static aerodynamics requirements.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents the greatest challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. Inspection presents another great challenge; Most mask rules are imposed not because of mask manufacturing constraints, but due to limitations of mask inspection tools. In addition, at the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs), ILT, and SMO are required. Their use results in significantly increased mask complexity, making mask defect inspection and disposition more challenging than ever. In this paper, a single computational lithography and computational inspection framework based on Level Set Method is presented and explained in non-mathematical language. Results at the 32nm node and below are presented which demonstrate the benefits of Level-Set-Method-based ILT and IIT in design rule optimization, SMO, full-chip correction, and mask inspection.

In the first implimentation by Luminescent of ILT-enabled Source-Mask Optimization (SMO), an ILT-optimized mask was generated for each designated illumination condition as the source was swept through various parameter settings in order to find the best combination of source and mask. This approach has been successfully applied to explore and select lithography processes and design rules for advanced semiconductor technology nodes. In Luminescent's latest implimentation of ILT-enabled SMO, the same Level Set Method used in the mask optimization is used in the source optimization; in other words, the source map is represented by a level set function. During the optimization process, the level set function evolves to achieve a minimized cost function, where the cost function is defined as the difference between aerial image and ideal image (MEEF and DOF can also be used in the cost function) via a gradient flow, and the gradient flow is based on the cost function itself. This flow is interlaceded with the mask inversion flow so that a simultaneous mask & source co-optimization is achieved. In this paper a number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of ILT-enabled SMO.

Model-driven target optimization using an ILT hotspot fixer is applied to line collapsing defects of 2- dimensional randomtest pattern of a very low K1 process. The target is moved by minimizing the process variation band and the pitches of hotspot points are relaxed.The image quality improvement is thenchecked. Model driven target optimized NILS and MEEF at the weakest hotspot point are improved to 1.22 and 5.5 from the values 0.79 and 10.6 of a traditional OPCwith advanced solver, respectively. The pattern collapsing hotspot is then validated to be repaired by optimizing target position. A full hotspot fixer flow including model-driven target optimization using ILT can also be extended into DFM applications.

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years, source optimization and mask pattern correction have been conducted as two separate RET steps. For source optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been introduced for the lithography development stage. The next important step would be the extension of SMO, and in particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO and its extendibility to full chip designs.

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance and need to be enabled for production as one of the leading candidates for low-k1 lithography. By the very nature ILT masks are computed, they could seem to be complicated to manufacture in production. In a prior publication [1], it has been shown at clip level that the Inverse Synthesizer (IS™) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT n eeds to be studied at full chip level with various aspects including mask data fracturing, MRC co nstraints, writing time, and inspection. The computation of ILT mask usually starts with the calcu lation of an optimized contoured mask then followed by manhattanization step to convert contour into horizontal-ver tical segments. By varying the segmentation length during manhattanization, it can affectively change the mask complexity while maintains the shape of mask. The result of segmentation length impact on writing time and lithography perfor mance at full-chip is presented. MRC is another important factor in mask manufacturability which needs to be carefully studied. Mask pattern transfer fidelity and inspectability at various selected MRC rules are also presented in the paper. Keywords: Inverse lithography technology (ILT), Sub-resolution assist feature (SRAF), Resolution enhancement technology (RET), Lithography simulation

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used.. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

Mask Error Enhancement Factor (MEEF) plays an increasingly important role in the DFM and RET flow required to continue shrinking designs in the low-k1 lithography regime. The ability to model and minimize MEEF during lithography optimization and RET application is essential to obtain a usable process window (PW). In Inverse Lithography Technology (ILT), MEEF can be included in the cost function as a nonlinear factor, so that the inversion minimizes MEEF, in addition to optimizing PW and edge placement error (EPE). ILT has been shown to optimize masks for a given source. Using ILT for contemporaneous Source and Mask co-Optimization (SMO) can provide further benefit by balancing the complexity of mask and source. Results demonstrating the benefits of "MEEF-aware" ILT and SMO for advanced technology nodes are presented in this paper.

As reticle line widths shrink and RET complexity increases, even a single sub-micron defect can reject a photomask. High-end reticle manufacturers striving for increased yield and reduced cycle times are relying on low incoming rawstock defect levels and handling via SMIF mini environments for critical manufacturing steps. However, even in SMIF compatible reticle fabs, human handling is often required to load or unload a reticle to/from a SMIF environment. In an effort to provide a fully integrated solution to manufacturing 65 nm and below photomasks, Photronics has introduced a blank inspection/management system developed by Hitachi High Technologies and Fortrend Engineering. The clustered system is capable of robotic transfers in conjunction with blank storage, inspection, and material tracking capabilities. It consists of four major systems: a horizontal mask blank transfer system with state-of-the-art blank sorting capability, an integrated Hitachi GM3000 Mask Blank Surface Inspection System, a totally self-contained and sufficient Mask Blank Storage Station, and a material logistic control software system for material management and SPC. The Fortrend Lamina sorting system has a bright light inspection module for gross particle contamination detection, and a robotic transfer module for mask exchanges between SMIF and other shipping/transport boxes employed in the mask manufacturing facilities. The clustered Hitachi inspection system is an integral part of the solution allowing for additional inspections of stored and incoming blanks by optically detecting foreign particles and pinholes. The data is transferred and stored in the Foretrend handling system control module and may be used for rawstock management and screening based on a predefined criteria. The integrated system provides a total solution to mask manufacturing challenges at 65 nm and below.

As photolithography is pushed to fabricate deep-sub wavelength devices for 90nm, 65nm and smaller technology nodes using available exposure tools (i.e., 248nm, 193nm steppers), photomask capability is becoming extremely critical. For example, PSM masks require more complicated processing; aggressive OPC makes the writing time longer and sometimes unpredictable; and, high MEEF imposes much more stringent demands on mask quality. Therefore, in order for any new lithography technology to be adopted into production, mask manufacturability must be studied thoroughly and carefully. In this paper we will present the mask manufacturability study on mask patterns created using Inverse Lithography Technology (ILT). Unlike conventional OPC methodologies, ILT uses a unique outcome-based technology to mathematically determine the mask features that produce the desired on-wafer results. ILT solves the most critical litho challenges of the deep sub-wavelength era. Potential benefits include: higher yield; expanded litho process windows; superb pattern fidelity at 90, 65 & 45-nm nodes; and reduced time-to-silicon - all without changing the existing lithography infrastructure and design-to-silicon flow. In this study a number of cell structures were selected and used as test patterns. "Luminized patterns" were generated for binary mask and attenuated phase-shift mask. Both conventional OPC patterns and "luminized patterns" were put on a test reticle side by side, and they all have a number of variations in term of correction aggressivity level and mask complexity. Mask manufacturability, including data fracturing, writing time, mask inspection, and metrology were studied. The results demonstrate that, by optimizing the inspection recipe, masks created using ILT technology can be made and qualified using current processes with a reasonable turn-around time.

It has been demonstrated that the write time for 50keV E-beam masks is a function of layout complexity including figure count, vertex count and total line edge. This study is aimed to improve model fitting by utilizing all the variables generated from CATS. A better correlation of R 2 = 0.99 was achieved by including quadratic and interaction terms. The vertex model was then applied to estimate write time of various nano-imprint templates. Accuracy of the vertex model is much better than the numbers generated from E-beam tool software. A 90nm test layout was treated with a mask optimization (MO) algorithm. A 26% write time reduction was observed through shot count reduction. The advanced features of the new generation E-beam writing tool combined with mask layout optimization, allows the same level of mask cost even though the capital cost of the new tool set increased 25%.

Long write times have been an industry wide concern regarding rising mask costs. The purpose of this study is to develop a simple model that can predict mask write time precisely, without an e-beam writer. With a good understanding of the trade-offs between design complexity and write time, mask makers can work with mask designers more closely to simplify design and minimize mask cost. This work compared several basic models including calculations based on write area with a fixed e-beam shot size, a software estimation with a pre-set exposure, and a mask stage settling time. Our proposed model uses a completely different approach to examine the correlation between layout complexity (vertices count, total line edge, figure, etc.) through a CATS layout segmentation and actual write time. It is found that write time is a strong function of layout figure, vertex count and total line edge. Errors between actual write time and estimated write time from the new model reduced from 7% on average on the current production software to 3%. Additionally, the new model can operate independent of the writer type and without fractured data being transferred onto a writer. Also provided are a few case studies to evaluate the interaction between write time and basic shape/OPC (optical proximity correction). Using a simple design shape and a better data snapping strategy can reduce write time up to 10 fold for applications in nano-imprint template manufacturing. Several strategies to reduce mask cost are proposed.

To accelerate the time-to-market of advanced photomasks, Photronics launched its 90nm program in spring 2003. The program included three learning cycles and a technology transfer phase. Both 90nm test masks and product masks from leading integrated device manufacturers (IDMs) and foundries were exercised through the cycles. Stringent success criteria were set based on a survey of leading customers’ requirements and the International Technology Roadmap for Semiconductors (ITRS). Hundreds of binary masks, embedded attenuated phase shift masks (EAPSMs), and alternating aperture phase shift masks (AAPSMs) were produced throughout the program. All targets were exceeded. This paper describes program success criteria, complexity of customer requirements, 90nm test vehicle design, and efforts on improving critical dimension (CD) uniformity and registration. Results in positive and negative chemically amplified resist (CAR) and tunable etching for AAPSM are shown. Details on AAPSM undercut optimization, intensity and CD imbalance are reported.

A comprehensive set of numerical, mask pattern operators is developed and applied for the purpose of understanding photomask fabrication tolerances supporting aggressive, optical lithography resolution enhancement. Using these numerical operators, the content and fidelity of the photomask is systematically degraded and wafer level results predicted using experimentally calibrated simulation. The concept of a mask sensitivity matrix is introduced and used as a bridge to full Monte Carlo analysis of photomask fabrication errors. A statistical approach to analyze mask defect tolerances for resolution enhancement options is presented within the same numerical framework. Such methodical and detailed analysis of mask construction parameters is a vital step toward understanding the complex interaction between mask quality and printed image and hence the delivery of 65 nm node lithography capability.