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An area-efficient voltage-sensing readout circuit employing chopped voltage-controlled oscillator (VCO)-based continuous-time delta-sigma modulator (CTDSM) is presented in this paper. This VCO-based CTDSM features direct connection to sensors to eliminate pre-amplifier for achieving better hardware efficiency. The VCO is designed as a trans-conductor current-controlled oscillator, which is a fully differential $G_{m}$ stage cascaded with two CCOs, to provide a high-input impedance to sense the voltage signals from sensors. Analysis shows that the main noise and offset contributor is the $G_{m}$ stage. This problem is mitigated by employing choppers at critical location within the circuit. The VCO-based CTDSM is implemented in a 40-nm CMOS process. The power consumption is $17~\mu \text{W}$ under 1.2-V supply. With a 4-mVp (8-mV $_{\textrm {pp}})$ input, it achieves 61.85-dB signal-to-noise-and-distortion ratio over a 5-kHz bandwidth and the total harmonic distortion is −70.8 dB. The input-referred noise is 32 nV/ $\surd $ Hz. The chip area is only 0.0145 mm $^{\textrm {2}}$ .

A VCO-based sensor readout circuit is presented. It comprises a VCO-based integrator with counters, and a capactively-coupled feedback DAC, to form a 1st-order DSM with high input impedance and wide dynamic range for voltage sensors. Chopping is applied to suppress the flicker noise. The time-domain approach relaxes the voltage swing requirement compared to that of a Gm-C integrator, and thus area efficiency is achieved. The prototype is implemented in 40nm CMOS. It consumes 21μA under 1.2V supply. With a 100mVpp sinusoidal input, it achieves 74.9dB SNDR over 2 kHz BW and the THD is −82dB. This readout circuit is also measured with a Hall sensor to demonstrate its operation. The FoM and distortion achieves the state-of-the-art performance of VCO-based sensor readout circuits.

A sensor readout circuit employing chopped VCO-based CTDSM is presented in this paper. This VCO-based ADC features direct connection to the sensors to eliminate pre-amplifier. The VCO is designed as a Gm-CCO, which is a G m stage cascaded with the folded-cascode current-controlled oscillator. The proposed circuit ensures a high input impedance. Furthermore, the main noise and offset contributor, the Gm stage, is mitigated by chopping operation. The VCO-based CTDSM is implemented in 40-nm CMOS. The whole circuit draws 14 μA from 1.2-V supply. With a 2.4-mVpp input, it achieves 49.43 dB SNDR over 5-kHz BW and has SFDR of 59.5 dB. The input-referred noise is 40nV/√Hz. The chip area is only 0.0145 mm2.

This paper presents an area-efficient and fast-response CMOS Hall sensor system for a camera autofocus system. The prototype comprises of a Hall sensor and a capacitively-coupled instrumentation amplifier (CCIA). The Hall sensor adopts the spinning current technique to mitigate the Hall element offset. In the CCIA, the T-capacitor network is employed considering the capacitor matching requirement and the chip area. The amplifier offset is further suppressed by a ripple-reduction loop. This chip is measured with Helmholtz coil, Solenoid, and NMR system. Implemented in a 0.18-μm CMOS process, it achieves 564 μT rms in 180-kHz BW. The linearity error is < 0.5% over ±100-mT range. The power consumption is 1.19 mW, and the area is 0.12 mm2.

A chopped capacitively-coupled instrumentation amplifier (CCIA) with a proposed duty-cycled Gm-C DC servo loop (DSL) for bio-potential signal acquisition is presented. The proposed architecture realizes a large time constant with small circuit area without sacrificing noise and power performance. Furthermore, this pseudo-resistor-less design grants this architecture easily portable for more advanced processes. Fabricated in a 0.18-μm CMOS, this chip draws 2.37 μA from a 1.8-V supply and occupies only an active area of 0.43 mm2. The total integrated noise from 0.5 to 100 Hz is 1.04 μVrms and results in a noise efficiency factor of 7.8.

This paper performs the detailed analysis and measurement of a pseudo-resistor based CCIA used for bio-potential signal acquisition. The pseudo-resistor is implemented with MOS transistors operating in deep sub-threshold region, whose characteristic is not well-modeled in simulation. The resistor value versus control voltage and the effect of leakage current at OPAMP input node are discussed and characterized in this paper. The tested chip consumes 1.3µA from a 1-V supply, and the total integrated noise from 0.5 to 100 Hz is 3.26µVrms. It achieves a noise efficiency factor of 14.6.

This paper presents a low-noise low-power Instrumentation Amplifier (IA) for ECG applications. Chopped capacitively-coupled IA (CCIA) is built to precisely define the gain and avoid flicker noise. The circuit for electrode offset (EOS) cancellation is implemented in feed-forward (FF) manner with an area-efficient SC integrator. The FF architecture uses less capacitor ratio to define the low HPF corner than the feedback architecture. Implemented in a 0.18-μm process, the circuit draws 4.2 μA from a 1.8 V supply, and occupies 0.63mm2. The total integrated noise from 0.5 to 100Hz is 7.37 μV rms .

This paper presents a readout circuit for piezo-resistive sensing applications. It is based on a resistor-based oscillator which converts the resistance information into frequency domain. In the readout circuit, a mixer is employed to down-convert the oscillator frequency to lower frequency for subsequent digitization. The frequency down-conversion operation is equivalent to amplification in time which increases the system sensitivity to resistance variation. A frequency calibration loop is incorporated to set the mixer output frequency to a well-defined initial value. The readout circuit is fabricated in a TSMC 0.35-μm Bio-MEMS CMOS process platform. The oscillation frequency is 24 MHz, and the down-converted output frequency at mixer output is set to 100 kHz. The total readout circuit consumes 1 mW with 3-V supply. The system sensitivity is 7 kHz/Ω.