1. Design and implementation of low power high-speed CMOS SOI circuit.
- Author
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Naik, R. Purushotham, Balaji, B., Murthy, A. Krishna, and Radhamma, E.
- Subjects
COMPLEMENTARY metal oxide semiconductors ,METAL oxide semiconductor field-effect transistors ,ENERGY consumption ,SUPPLY & demand ,LOGIC circuits - Abstract
This paper explores the effect of scaling for low energy and high efficiency of demand and as difficulties of SOI circuits designing. This paper presents a 45-nm SOI MOSFET design and surveys the effect on various instrument parameters of the variant of channel doping and gate oxide thickness. Characteristics have been acquired for the suggested MOSFET by considering the most helpful channel doping and TOX values. The Visual TCAD system is used to simulate devices and extract parameters. In 180nm technology, the circuit is built with the Cadence Virtuoso tool. Existing designs such as complementary pass transistor logic, transmission gate adder, and transmission function adder, and others were compared in terms of power and layout space. Static power consumption for 1.8V supply is 477.3 pW, and average power consumption is 3.617 w, which is significantly less than previous designs. Even the layout has been applied, and DRC, LVS, and RC extraction have been completed. In terms of power and layout, this design is superior to the previous designs. [ABSTRACT FROM AUTHOR]
- Published
- 2022
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