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High-speed data communication is becoming essential for many applications, including satellite communication. The security algorithms associated with the communication of information are also required to have high-speed for coping up with the communication speed. Moreover, the Authenticated Encryption (AE) algorithms provide high-speed communication and security services include data encryption, authentication, and integrity. The AE algorithms are available with serial and parallel architectures; among them, the Galois Counter Mode (GCM) algorithm has a parallel architecture. The Synthetic Initialization Vector (SIV) mode in the AES-GCM-SIV algorithm provides the nonce misuse protection using the GCM algorithm. Besides, reduced data throughput is provided using the AES-GCM-SIV algorithm as compared to the AES-GCM algorithm. This work introduced a parallel algorithm with re-keying and randomization of the initialization vector for high data throughput, nonce misuse protection, and side-channel attack protection. The implementation of the proposed algorithm is performed on Field Programmable Gate Array (FPGA) and it’s compared with the FPGA implementations of AES-GCM, AES-GCM-SIV, and recently introduced algorithms. The optimization of the proposed algorithm and security analysis is presented for space application using different optimizations and a combination of optimizations.

Recently, the security of public key security algorithms have been research extensively; besides, the utilization of public key cryptography requires key exchange protocol. The security of key exchange protocol is significant as it transmits the key and therefore, the security of public key algorithms depend on the security of key exchange protocol. In addition, the concept of Perfect Forward Secrecy (PFS) is evolving with the number of security threats. Traditionally, the key exchange protocols use asymmetric and symmetric to exchange session keys, which consumes more hardware resources and time for implementation. Moreover, these encryption based key exchange protocols requires several messages to exchange before sending the key, which cause delay in key exchange and consume bendwidth ineffciently. This work provides a new key exchange protocol with randomized initialization vector and advanced features for PFS. The proposed algorithm is simple and faster as compared to previous algorithms, the security of proposed algorithm is comparable to One Time Pad (OTP) algorithm.

The increase in the flow of information and high-speed communication has compelled researchers to use satellite networks for different applications. The satellite networks comprise different satellites in different orbits that require the data security algorithms for the providing security and privacy of consumers' information. The data security primarily consists of data confidentiality service, which is provided by data encryption algorithms. The data encryption algorithm for example AES algorithm is utilized in many applications, including the satellites. The challenges for AES algorithm utilization in satellite applications are high-speed computation, lightweight implementation, and catering the radiations in the space environment. In this work, optimizations are proposed for coping with the challenges in a data encryption algorithm for the space environment. Also, the high-throughput optimization for the AES algorithm is realized on FPGA, and it equated with previous work. Moreover, the recent security attacks, for instance the nonce misuse attack is challenging for the security of encryption algorithms. The high-throughput optimized encryption algorithm protects against the recent attacks by the modifications in the AES algorithm. Moreover, the security analysis is provided against the latest attacks for the validation of high-throughput optimizations.

Satellite communication is among those applications where data confidentiality is required, but at the same time, computational resources are limited as well as the delay is critical. For these types of applications, symmetric key encryption algorithms are preferred over asymmetric key algorithms, due to lower computational cost and faster speed of operation. Furthermore, due to various critical aspects of information security, using Perfect Forward Secrecy (PFS) in many communication applications is advantageous. There are two ways to achieve PFS; either a mechanism for new key generation is required, or some protocols are used for sharing new session keys before communication. Both of these ways, at minimum, append additional computational load and delay in communication, which are critical in satellite communication. This is probably the most significant barrier that satellites do not use PFS for every communication. This paper presents a novel encryption algorithm where a message key is generated such that later only Exclusive OR (XOR) operation can be used to produce the ciphertext. Hence, the proposed algorithm eliminates the need for two separate algorithms for message key generation and encryption for PFS. Security analysis and experimental results show that proposed encryption algorithm is not only secure but also faster and cheaper than the widely used AES-CTR encryption algorithm. Therefore it is suitable to be used in satellite communication for PFS.

Advance Encryption Standard (AES) is an algorithm widely used for encryption, authentication, authenticated encryption as well as in security protocols for providing security services in many modern-day applications. The primary reasons for the extensive use of AES are its stronger security and faster speed than its competitors. In the AES algorithm, different keys derived from the main key are used in encryption rounds, to provide strength to the security of the algorithm. However, in standard AES key expansion algorithm, the sub-keys are derived sequentially, that is one after other. This dependence on the previous sub-key has two problems. Firstly, the key generation cannot be parallelized, secondly, if any single sub-key is known to the attacker, all the other sub-keys, including master key, can be extracted. Also, Differential Power Analysis attack is known effective on standard AES key schedule. In this paper, we proposed a new key parallelized expansion algorithm for AES. The proposed algorithm removes the dependence on other sub-keys to provide faster speed and enhanced security. The proposed algorithm has been implemented in MATLAB software and on FPGA. The results of implementation validate that the computational efficiency of the proposed algorithm is superior to standard AES Key expansion.

The growing number of threats and attacks on communication systems has encouraged researchers to identify methods for providing security for data communication. Besides the encryption and authentication algorithms provide data security services for communication systems. However, the recent attacks on communication systems reveal that the attacks utilize the analysis of plaintext/ciphertext to breach the security of communication systems. Therefore, the plaintext should be randomized to prevent correlation between ciphertext. In this work, an algorithm is proposed for increasing ciphertext randomness in Parallel Cipher-based Message Authentication Code (PCMAC) Algorithm. The proposed algorithm utilizes the high throughput of PCMAC authenticated encryption algorithm for providing high throughput and more randomized ciphertext. The proposed algorithm is implemented for generation of Initialization Vector (IV) using the GEFFE generator and right shift operation for creating randomness in the ciphertext. The comparisons result show that the proposed implementation is more randomized as compared to the previous implementation.

In the present, the use of communication systems is not a luxury but a necessity. The growing reliance on technology and its uses in all walk of life have realized the need for robust security systems for communication. The Advanced Encryption Standard (AES) in Counter (CTR) mode support high-speed operations due to parallel architecture and having no feedback or chaining mode. The AES-CTR algorithm involves encryption of Initialization Vector (IV) with a secret key for generation of ciphertext. A unique IV is required in the AES-CTR algorithm for maintaining the secrecy of data and generation of unique ciphertext. Previously, the researchers utilized the GEFFE generator for generation of IV as well as right-shift and increment operation were used for IV generation. The combination of these two algorithms can provide an increase in ciphertext randomness as compared to using it individually. In this work, we have proposed an IV generation algorithm based on the GEFFE generator and right-shift and increment operation for the AES-CTR algorithm. The proposed algorithm generates an increase in randomness for data security. The comparative analysis with other techniques shows that our algorithm has better in performance and security.

The evolution in digital communication technology has provoked the need for providing efficient security services for communication. The data security services majorly includes; confidentiality, authenticity, and integrity services. The Authenticated Encryption (AE) algorithm provides all these three services. Initially, AE algorithms were proposed with serial architecture. These AE algorithms are low throughput as compared to parallel architecture algorithms such as Galois Counter Mode (GCM) algorithm. In this work, we have presented a new AE algorithm with parallel architecture named as Parallel Cipher-based Message Authentication Code (PCMAC). The PCMAC AE algorithm is consists of Advanced Encryption Standard (AES) algorithm in Counter mode (CTR) and parallel implementation of the CMAC authentication algorithm. The proposed PCMAC algorithm is implemented on FPGA for showing its utility for high throughput applications. In this work, we compared the PCMAC AE algorithm implementation with the GCM AE algorithm implementation. The experimental results show that the throughput of PCMAC algorithm for pipelined implementation is 41.45 Gbps.

During the last decade, the development of space technology for the benefits of humanity has been a significant area of research. The communication systems used in space technology is more sensitive to environmental effects than that used on earth. As in space, communication systems should withstand radiations, pressure, and vacuum effects. Therefore, the different types of radiations exposed to electronic hardware in space can cause anomalies in communication systems. Such anomalies can cause loss of data and even damage to equipment due to effects known as Single Event Effects (SEE). The security services in space are provided using encryption algorithms such as Advanced Encryption Standard (AES). In the AES algorithm, the Substitution Box (S-Box) implementation generally utilizes memory blocks. These memory blocks are mostly affected by SEE in the presence of radiations. There are two main techniques for implementing the S-box for the AES algorithm either by generating a predefined table or using an algorithm-based architecture for substitution. In this paper, we have analyzed the pros and cons of using these architectures for the implementation of the S-Box on FPGA. Moreover, experimental results show that the algorithm-based architectural implementation is more SEE tolerant and more suitable for satellite application.

In communication systems, data encryption and authentication algorithms are utilized for secure communication. The utilization of encryption and authentication algorithms depends on the field of application and required level of security. Recently, researchers are working on encryption based authentication algorithms, as both services of encryption and authentication are utilized in highly secure systems such as satellite communication. The Cipher based Message Authentication Code (CMAC) finds its relevance in many applications. CMAC algorithm has been implemented previously on software and hardware. But by assessment of previous work on hardware implementation it seems that competence could be enhanced by efficiently utilizing hardware resources. In this paper, an improved and efficient hardware implementation of CMAC algorithm on FPGA is proposed for satellites application. Our results showed improvement in consumption of FPGA area and time utilization as compared to previous implementations.

In this era of information technology, information security is a major concern. To address the challenges of data security, cryptography is used for storage as well as for the communication of data. A cryptographic algorithm has two main performance characteristics: the ability to secure data against different attacks and the processing speed. An algorithm is considered secure if no attack exists to reveal the original contents without knowing the key. The strength of any secure encryption algorithm is, therefore, generally measured based on the difficulty to obtain the encryption key through cyber-attacks such as brute force. It is presumed that the bigger the key size, the more difficult it is for the attacker to compute the key. Consequently, increasing the key size generally increases the computational complexity and processing time of algorithms. As a result, an established assumption is the existence of a tradeoff and computational complexity. In this paper, we are presenting an alternate symmetric key encryption algorithm, which can easily avoid long and complex computation of conventional popular symmetric key encryption algorithms such as the Data Encryption Standards and the Advance Encryption Standard. We have shown that despite providing a higher level of security, one simplest software implementation of our algorithm is faster than some previously implemented conventional algorithms. Additionally, our algorithm also provides other advantages such as inherent data compression option and flexibility of choosing different complexity levels according to the need for different applications.

In this paper, a new scheme to enhance security of wireless gateway node is presented. In proposed scheme, analysis of implementing counter with cipher block chaining message authentication code on field programmable gate array has been proposed. Preliminary results show that proposed scheme does not have application dependency and have potential to be integrated with any application of wireless sensor network.