1. MCAPI-compliant Hardware Buffer Manager Mechanism to Support Communication in Multi-Core Architectures
- Author
-
Thomas Mesquida, Fabien Clermidy, Romain Lemaire, and Thiago Raupp da Rosa
- Subjects
Hardware architecture ,Multi-core processor ,business.industry ,Computer science ,MCAPI ,Interface (computing) ,Programming complexity ,02 engineering and technology ,020202 computer hardware & architecture ,Software ,Embedded system ,Synchronization (computer science) ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,business ,Computer hardware - Abstract
High performance and high power efficiency are two mandatory constraints for multi-core systems in order to successfully handle the most recent applications in several fields, e.g. image processing and communication standards. Nowadays, hardware accelerators are often used along with several processing cores to achieve the desired performance while keeping high power efficiency. However, such systems impose an increased programming complexity due to the lack of software standards that supports heterogeneity, frequently leading to custom solutions. On the other hand, implementing a standard software solution for embedded systems might induce significant overheads. This work presents a hardware mechanism in co-design with a standard programming interface (API) for embedded systems focusing to decrease overheads imposed by software implementation while increasing programmability and communication performance. The results show gains of up to 97% in latency and an increase of 40 times in throughput for synthetic traffics and an average decrease of 95% in communication time for an image processing application.
- Published
- 2016