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This work presents a novel hybrid compression architecture that seamlessly combines the advantages of an embedded test compression technique with a lightweight codewordbased compression scheme. Embedded test compression has proven to be beneficial and is widely used in industrial circuit designs. However, particularly, in test applications within lowpin-count environments, a certain number of test patterns is incompressible and will, therefore, be rejected. This leads to a test coverage decrease which, in turn, jeopardizes the zero defect policy of safety-critical applications like automotive microcontrollers. Therefore, the rejected test patterns are typically transferred in an uncompressed way bypassing the embedded compression, which is extremely costly. The proposed hybrid architecture mitigates the adverse impact of rejected test patterns on the compression ratio as well as on the test application time of state-of-theart techniques. The experimental evaluation of industrial-sized designs clearly shows that a significant compression ratio up to 67.4% and a test application time reduction up to 72.9% can be achieved when utilizing the existing multi-channel interfaces.

Technology scaling made possible to increase IC capabilities from one node to the next by adding more transistors within the same die area while keeping a low pin count. As a consequence, test complexity increased exponentially, requiring engineers to use not only better test pattern generation software, but also powerful and expensive Automatic-Test-Equipments (ATE), usually not viable and accessible for small fabless start-ups and universities. In this work, we propose a low-cost and flexible ATE intended for manufacturing tests of the digital part of a multi-million gate industrial mixed signal ASIC produced in a 130nm technology that will be used at CERN in the ALICE experiment. The proposed ATE was built upon a ready-to-use platform including an embedded ARM-based processor and a FPGA to effectively apply the test vectors via the Device-Under-Test (DUT) scan chains in a feasible time and viable cost without the need for a PC. The ATE was operated to execute in-series manufacturing tests on two versions of the SAMPA chip, allowing identifying on-silicon defects.

Test cost reduction is necessary to test a complex System-on-a-Chip(SoC) which adopts various Intellectual Properties (IP). In this paper, test architecture with low pin count which is able to IP-based SoC test, using IEEE Std. 1149.7 and IEEE Std. 1500, is proposed. IEEE Std. 1500 provides independent access mechanism for each IP in IP-based SoC test. In this paper, just two test pins are required by composing that these independent access mechanism can be controlled by IEEE Std. 1149.7. The number of Chips which are tested at the same time is increased by reducing required test pin count at wafer and package level test, and consequently the overall manufacturing test cost will be reduced significantly.

Recently, we must use the various scan test techniques for various purposes, for example, compression scan or LBST for mass-production test, LBIST for field test, legacy scan for fault diagnosis, and so on. Moreover, the number of the available external scan pins is different in each test process, for example, the parallel test process has a low pin count, the assembled chip test process has several pin counts depending on the assembled package types, and so on. Then, the cost-effective scan chain structure is also different for each purpose and each test process. In order to correspond to this situation, we introduce the multi-configuration scan structure which can change the numbers of scan chains. Evaluation result shows that our approach can improve test time for area overhead.

This paper presents a novel approach for performing diagnosis in test access mechanisms (TAM) architectures based on time domain multiplexing and serial scan shifting. These TAM architectures allow efficient application of low power compressed patterns to individual embedded cores present in SoCs using limited pins. The proposed diagnosis approach relies on the connectivity information of the TAM architecture to map SoC level failures to a particular embedded core. These TAM architectures allow high level of diagnosis resolution and performance.

The VL86C010 processor, which is well suited to RISC applications because of its small die size, low power dissipation, and low pin count, is presented. This RISC processor family was designed for maximum system performance at minimum cost, rather than maximum CPU performance at any cost. The components of the system CPU, memory controller, IO controller, and video controller were partitioned to take advantage of less-expensive plastic IC packages and, more importantly, less-expensive dynamic RAM devices (DRAMs) by using their page mode of operation. These components are described, and the processor performance is examined. >

The dramatic price reduction of NAND Flash devices in recent years has created an opportunity for Flash to penetrate mass storage applications. This will happen provided the memory vendors can deliver NAND Flash devices with adequate performance and no intrinsic cost premium over the lowest cost conventional NAND Flash devices. The new HLNAND Flash Architecture facilitates this transition by enabling high performance NAND Flash devices with increased longevity and a cost advantage stemming from the low pin count interface and small die size.

This chapter describes Trusted Computing Group (TCG) Main Specification modifications in regard to migration from a Trusted Platform Module (TPM) 1.1-based to a 1.2-based host system design. There are major modifications to the Main Specification and an introduction of totally new concepts, in addition to a completely new Low Pin Count (LPC)-based Trusted Interface Specification (TIS). The TIS adds a new concept concerning the physical and logical interface with regard to the LPC bus, and also introduces the concept of localities or entities that have different priority levels within the TPM device itself. Using the TIS interface, the TPM can distinguish between hardware, operating system, and application command requests. The most profound difference between the Version 1.1 and 1.2-based TPM realizations is found at the device driver layer, and concerns both the physical and the logical aspects based on the TPM LPC interface. It is noted that the Version 1.1-based commands augment and extend the Version 1.2-based Command Suite.

The capability of the Command Suite with regard to the Trusted Platform Module (TPM) is useless, without a means to communicate with the TPM. This can be achieved with the help of a well-defined Application Programming Interface (API). The Trusted Device Driver essentially gives the ability to communicate concerning the TPM physical interface and logically through a well-defined driver API. Atmel produces the only TPM with System Management Bus (SMBus) communication support. All the other flavors of TPM communicate via the Low Pin Count (LPC) interface. The LPC bus is a proprietary protocol that is generally associated with PC motherboard design. This chapter focuses on SMBus communication. The Trusted Device Driver Library (TDDL) contains the TCG-defined API, which allows any TCG Software Stack (TSS) secure stack to gain access to the TPM Command Suite via a well-defined and predictable software interface. The TDDL also contains information about how to communicate with specific vendor's TPM.

Product miniaturization is driving the industry to introduce smaller form factor products-typically, chip-scale or chip-size packages (CSPs). Applications include consumer products such as digital camcorders and cameras; mobile phones and other handheld communications products; IC and memory cards; and portable computers. In addition, CSPs are finding their way into products where increased density is critical. CSPs offer many of the advantages of bare die-tested die, size, weight, and low profile-but at the same time provide a packaged solution. Low pin count devices are increasingly being packaged in CSPs, with larger volumes shipping every year. More than 100 CSP varieties have been introduced and many versions are shipping in high volume. This stimulates questions as to which packages are in high volume use for each application; which applications use the ultimate CSP, the wafer level packages; what the drivers are for these packages in each application area; what products will be seen in the future; and how packages will change to meet the needs of these products. This paper addresses these questions by examining the trends in CSPs and the high volume applications driving the explosion of growth in this emerging area.

The continued emphasis on higher-density (smaller) and better-performance (faster) on electronics system design makes the board (PCB layout) design become more complex and usually will challenge the DFM guidelines currently applied by the industry. For example, the design of mirrored BGAs on double-sided board, which is not recommended by current industry DFM guidelines, due to the real estate constraint. In fact, there are several successful design applying low pin count mirrored or staggered BGAs or CSPs for certain applications, such as memory modules.

Publisher Summary Together, disk operating system (DOS) and the read-only memory basic I/O system (ROM BIOS) perform all of the operating system functions necessary to support the personal computer (PC), such as managing directories and files, displaying text and graphics, and loading and executing programs. They also perform tasks that one might not be aware of, such as determining the type of equipment installed in a PC or formatting a hard disk. The ROM BIOS houses all of the low-level routines for controlling I/O operations. The DOS routines, on the other hand, operate at a higher level than the ROM BIOS routines. Some of the DOS routines make calls to the ROM BIOS. Thus, if one is concerned about the performance of a program that one is writing, one should use the ROM BIOS directly. QuickC provides a complete set of built-in functions for accessing both DOS and the ROM BIOS. The chapter presents most of the major functions that are available. These functions are divided up into three main categories: general DOS interrupt calls, BIOS interrupt calls, and general interrupt calls which allow to access either DOS or the ROM BIOS.