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4H-SiC is a wide-bandgap material that exhibits excellent high-temperature conductivity and high operating voltage. These characteristics can provide high electrostatic discharge (ESD) robustness in high voltage applications. However, a considerably wide range of snapback phenomena is triggered for 4H-SiC-based ESD protection devices owing to a high critical electric field. In this study, an ESD protection device based on a lateral insulated-gate bipolar transistor (LIGBT) with a new structure that creates an internal silicon-controlled rectifier (SCR) path is proposed. The proposed ESD protection device minimizes the effective base region of the NPN parasitic bipolar transistor to the gate length based on the internal SCR operation of the LIGBT. It also adjusts the emitter injection efficiency of the PNP parasitic bipolar transistor by introducing a segment topology and inserting an additional implant area. Consequently, the proposed ESD protection device significantly improves the wide range of snapback phenomena occurring in the 4H-SiC materials. A conventional SCR, the LIGBT, and the proposed protection device were fabricated using the 4H-SiC process under the same condition, and their electrical characteristics were comparatively analyzed using a transmission-line pulse system. Moreover, its high-temperature reliability was evaluated at 300–500 K to examine the compatibility with 4H-SiC devices and circuits that require a relatively high-temperature operation.

The excellent area efficiency of dual-directional SCRs (DDSCRs) have made them desirable for low-voltage and high-voltage applications. However, to implement the required symmetrical structure, conventional DDSCRs have to lengthen their ESD discharge path. In addition, the low holding voltage of existing DDSCRs is not suitable for high-voltage applications. In this study, a novel DDSCR with a high holding voltage and low dynamic resistance is proposed and its electrical characteristics are verified. The proposed DDSCR has two additional internal parasitic bipolar transistors compared to a conventional low-triggering voltage DDSCR (LTDDSCR). Self-gate biasing reduces latch-mode feedback between the parasitic bipolar transistors in the SCR. The device is fabricated using 0.13 um BCD processes and implements a segment layout resulting in a very low dynamic resistance of 2.2 Ω and excellent holding voltages of up to 17.2 V. The proposed DDSCR demonstrates improved reliability and area efficiency for 12 V applications.

In this letter, a new silicon-controlled rectifier (SCR) structure fabricated using 4H-SiC materials has been proposed and investigated. The proposed structure alleviates the strong-snapback phenomenon that occurs in the 4H-SiC SCR and demonstrates low trigger voltage and high holding voltage characteristics. The proposed device exhibits improved snapback characteristics with very high holding voltage against electrostatic discharge surges owing to the structural features and application of segment topology. It also has excellent on-resistance and improved thermal reliability owing to the physical characteristics of 4H-SiC. Traditional SCR and low-voltage trigger SCR (LVTSCR) are fabricated with 4H-SiC under the same conditions and their electrical characteristics are comparatively analyzed with those of the proposed SCR. This study also evaluates the electrical characteristics at high temperatures (300–500 K) to verify the high- temperature reliability of the proposed structure. [ABSTRACT FROM AUTHOR]

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic‐diode‐triggered silicon controlled rectifier. The breakdown voltage and trigger voltage (Vt) of the proposed ESD protection circuit are improved by varying the length between the n‐well and the p‐well, and by adding n+/p+ floating regions. Moreover, the holding voltage (Vh) is improved by using segmented technology. The proposed circuit was fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS process with a width of 100 μm. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the Vt of the proposed circuit increased from 14 V to 27.8 V, and Vh increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human‐body‐model surges at 7.4 kV and machine‐model surges at 450 V.

• This paper proposes a novel SCR with high robustness and latch-up immunity. • By incorporating a surface current diverting path into the traditional SCR, the ESD characteristics of the proposed device are significantly improved. • Through 2D device simulation, the ESD characteristics of three SCRs are compared. • Vt1 (22.9 V), Vh (13.64 V) and It2 (18.49 A) of the PGSCR meet the requirements of the target chip. In an industry-level bus, strong electrostatic interference seriously threatens the reliability of chips. However, the holding voltage (Vh) and robustness of traditional silicon-controlled rectifier (SCR) cannot meet the electrostatic discharge (ESD) window of industry-level applications. To better cope with extreme environments, this paper proposes a novel SCR with high robustness and latch-up immunity for on-chip ESD protection of the industry-level RS485 bus. By incorporating a surface current diverting path into the traditional SCR, the ESD characteristics of the proposed device are significantly improved. Through two-dimensional device simulation, the ESD characteristics of traditional SCR, proposed P-Well Floating SCR (PFSCR) and proposed P-Well Grounded SCR (PGSCR) are compared, with a focus on exploring the role of surface discharge path. Three types of SCR are realized based on the 0.18 μm BCD process. The transmission line pulse (TLP) test results show that PGSCR (13.64 V) has a higher Vh and higher robustness than traditional SCR (2.13 V) and PFSCR (4.39 V). In addition, the trigger voltage (Vt1:22.9 V) and failure current (It2:18.49A) of the PGSCR fully meet the ESD window of the target chip. [ABSTRACT FROM AUTHOR]

In this paper, an electrostatic discharge ( ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ( Vt) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding n+/p+ floating regions. Moreover, the holding voltage ( Vh) is improved by using segmented technology. The proposed circuit was fabricated using a 0.18-μm bipolar- CMOS- DMOS process with a width of 100 μm. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the Vt of the proposed circuit increased from 14 V to 27.8 V, and Vh increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V. [ABSTRACT FROM AUTHOR]

In this Letter, an enhanced bidirectional modified lateral silicon‐controlled rectifier (EBMLSCR) is proposed for advanced dual‐directional electrostatic discharge (ESD) protection applications. The ESD characteristics of the novel EBMLSCR and conventional bidirectional modified lateral silicon‐controlled rectifier (BMLSCR) are measured using the transmission line pulsing tester. Compared with the BMLSCR, the EBMLSCR owns a lower trigger voltage down to 7.7 V, a higher failure current up to 6.5 A, a suitable holding voltage as well as the same superior leakage current. Based on these advantages, the proposed EBMLSCR can provide an effective ESD protection for the advanced 2.5 V/3.3 V input/output circuits, while the traditional BMLSCR becomes invalid for these applications due to its high trigger voltage and low robustness. In addition, the impact of some critical dimensions of the EBMLSCR has also been evaluated to further optimise the device performances. [ABSTRACT FROM AUTHOR]

A silicon-controlled rectifier (SCR)-incorporated BJT with high holding voltage is developed for electrostatic discharge (ESD) protection in a 0.6 \mu\m high-voltage 10 V process. This device consists simply of a floating \P^+ diffusion incorporated in a parasitic NPN BJT. A robust 6–7 kV ESD threshold and high-latchup-immune holding voltage of 15–18 V can be achieved by layout optimization of the NPN- \N^+-collector to floating \P^+-diffusion spacing and the floating \P^+ diffusion width. It can be equivalently regarded as parallel connection of an incorporated PNPN SCR part and an NPN BJT part. The incorporated SCR part is further composed of a parasitic SCR in series with a reverse-biased PN diode formed by the floating \P^+ region and N-well. The further analysis shows that the floating \P^+ diffusion is the key part of this SCR-incorporated BJT. The parasitic reverse-biased PN diode sustains most of the high holding voltage. The parasitic NPN BJT plays a major role in ESD current conduction, while the incorporated SCR in series with the reverse-biased PN diode is the secondary conduction path. [ABSTRACT FROM PUBLISHER]

The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions. [ABSTRACT FROM PUBLISHER]

In this letter, a novel high latch-up immunity electrostatic discharge protection device that can be equivalent to a PNP-type bipolar junction transistor (BJT) and a series-connected Zener diode is proposed. For the proposed device, the emitter of its BJT is formed by Zener implantation instead of conventional P-plus. In this way, the high latch-up immunity can be achieved by the Zener implantation dose and window designing. Meanwhile, the proposed device exhibits excellent voltage clamp capability and 2.2 times large second breakdown current as a generally used diode. [ABSTRACT FROM PUBLISHER]

Abstract: The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8V and a high trigger current of greater than 120mA. The robustness has measured to HBM 8kV (HBM: human body model) and MM 400V (MM: machine model). The proposed device has a high-level It2 of 52mA/μm approximately. [Copyright &y& Elsevier]

To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU) under the system-level electrostatic discharge (ESD) test for electromagnetic compatibility (EMC) regulation, an efficient component-level TLU measurement setup with bipolar (underdamped sinusoidal) trigger is developed in this paper. A current-blocking diode and a current-limiting resistance, which are generally suggested to be used in the TLU measurement setup with bipolar trigger, are investigated for their impacts to both the bipolar trigger waveforms and the TLU immunity of the device under test (DUT). All the experimental results have been successfully verified with device simulation. Finally, a TLU measurement setup without a current-blocking diode but with a small current-limiting resistance, which can accurately evaluate the TLU immunity of CMOS ICs with neither overestimation nor electrical-over-stress damage to the DUT during the TLU test, is suggested. The suggested measurement setup has been verified with silicon-controlled-rectifier test structures and real circuitry (ring oscillator) fabricated in 0.25-mum CMOS technology [ABSTRACT FROM PUBLISHER]