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Your search keyword '"Flip chip packaging"' showing total 4 results
Start Over Descriptor "Flip chip packaging" Topic electronics packaging
4 results on '"Flip chip packaging"'

1. High-Efficiency Revolving-Turret Chip Transferring Technology for Flip Chip Packaging.

Author

Hong, Jinhua, Xu, Zhoulong, Chen, Jiankui, and Yin, Zhouping

Subjects
*MILITARY airplanes, *INTEGRATED circuits, *INFORMATION technology, *ELECTRONICS packaging, *MICROELECTRONICS, *TURRETS
Abstract

With the rapid growth of the microelectronic packaging market, it is necessary to increase the throughput and reduce the cost of flip chip. Driven by these evolutions, a novel revolving-turret chip transferring (RTCT) technology is introduced to implement high-throughput flip chip packaging. The unnecessary time delays of packaging processes could be eliminated in the RTCT technology due to its parallel manner of motions. In order to analyze the packaging efficiency, the layout and movement sequence of the packaging system are studied, and a calculation model of packaging efficiency is proposed. Furthermore, the effects of the critical parameters (the horizontal and the vertical spacing of antennas and the maximum velocity and acceleration of the turret-type head) on packaging efficiency are investigated to search out the optimal parameters combination. To verify the performance of the RTCT technology under optimal parameters combination, two cases are implemented and compared. The results show that due to parallel motions of processes, unnecessary delays affecting the packaging efficiency have been reduced, and the packaging efficiency of ALN-9714 inlay could be more than 35k chips per hour. In addition, compared with the conventional flip chip packaging process, the RTCT technology is more effective in packaging the chips on antennas with multicolumn layout and small horizontal spacing. [ABSTRACT FROM AUTHOR]

Published
2018
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2. The prediction of failure probability in anisotropic conductive adhesive (ACA).

Author

Chao-Ming Lin, Ming-Horng Su, and Win-Jin Chang

Abstract

This paper develops a model for predicting the failure probability of flip chip packaging using anisotropic conductive adhesive (ACA). The proposed approach modifies the box model to improve the accuracy of the bridging probability estimation by considering bridging in all directions. In the current failure analysis, probability theory is applied to calculate the probability of both opening and bridging failure. The Poisson distribution is used to calculate the probability of opening in the vertical gap between the pads, while the modified box model is used to estimate the probability of bridging between the pads. The results indicate that the modified box model provides an effective means of accurately estimating the probability of failure. The failure analysis takes the volume fraction of the conductive particles as the major variable in defining the optimal ACA design condition. A V-shaped curve model can be employed to establish an appropriate value of the volume fraction as a function of conductive particle radius, pitch, and pad dimensions such that the overall probability of failure is minimized. [ABSTRACT FROM PUBLISHER]

Published
2005
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3. Substrate noise generation in complex digital systems: Efficient modeling and simulation methodology and experimental verification

Author

Heijningen, M. van, Badaroglu, M., Donnay, S., Gielen, G.G.E., and Man, H.J. de

Subjects
Substrates, Application specific integrated circuits, Hardware_PERFORMANCEANDRELIABILITY, Computer simulation, CMOS integrated circuits, Flip chip devices, Spurious signal noise, Computer Science::Hardware Architecture, Mixed analog-digital integrated circuits, Integrated circuit modeling, Substrate noise, Hardware_INTEGRATEDCIRCUITS, Flip chip packaging, Software Package SPICE, Gates (transistor), Electronics packaging, Interference, Crosstalk, Electric power supplies to apparatus, Fast Fourier transforms
Abstract

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.

Published
2002

4. Substrate noise generation in complex digital systems: Efficient modeling and simulation methodology and experimental verification

Subjects
Substrates, Application specific integrated circuits, Hardware_PERFORMANCEANDRELIABILITY, Computer simulation, CMOS integrated circuits, Flip chip devices, Spurious signal noise, Computer Science::Hardware Architecture, Mixed analog-digital integrated circuits, Integrated circuit modeling, Substrate noise, Hardware_INTEGRATEDCIRCUITS, Flip chip packaging, Software Package SPICE, Gates (transistor), Electronics packaging, Interference, Crosstalk, Electric power supplies to apparatus, Fast Fourier transforms
Abstract

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.

Published
2002

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