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The problem of survival memory management of a Viterbi decoder (VD) was solved by introducing a novel pointer implementation for the register exchange method, where a pointer is assigned to each row of memory in the survivor memory unit (SMU). The content of the pointer which points to one row of memory is altered to point to another row of memory, instead of copying the contents of the first row to the second. In this paper, the one-pointer VD is proposed; if the initial state of the convolutional encoder is known, the entire SMU is reduced to only one row. Because the decoded data bits are generated in the required order, even this row of memory is dispensable. Thus, the one-pointer architecture, referred to as memoryless VD (MLVD), reduces the power consumption of a traditional traceback VD by approximately 50%, but has some performance degradation. A prototype of the MLVD with a one third convolutional code rate and a constraint length of nine is mapped into a Xilinx 2V6000 chip, operating at 25 MHz with a decoding throughput of more than 3 Mbps and a latency of two data bits. Index Terms--Low power, memoryless, register exchange (RE), Viterbi decoder (VD), wireless.

The performance benefits of speculation in a release consistently software distributed shared memory system are examined. Speculative Home-based Release Consistency (SHRC) protocol is implemented for speculatively updating data at remote nodes for reducing the latency of remote memory accesses.

The problem of testing shared memories for memory coherence and consistency is studied where first it is proved that detecting violations of coherence in an execution is NP-Complete and it remains NP-Complete for a number of restricted instances. The results indicate that the complexity of verifying consistency models is not a mere consequence of coherence and verifying sequential consistency remains NP-Complete even after coherence is verified.

The five options for virtual address translation in the context of Distributed Shared Memory multiprocessors including Cache-Coherent Non-Uniform Memory Access Architectures and Cache Only Memory Access Architectures are described and compared. The Translation Lookaside Buffer is very effective when it is merged with the shared memory, because of the sharing and prefetching effects and there is no need to maintain its consistency is also observed.

An analytical approach and numerical simulation of rate equations yielded a memory diagram, and also demonstrated that pattern effects present at the output of the laser can be prevented by reducing the bias current to a level slightly below the threshold. An increase in the bias current induces an elevated bias of the laser above the threshold. The memory region comprises small no memory zones termed 'no-memory islands.'

In this paper, the algorithm and architecture of a variable-length-code (VLC) codec system using a new group-based approach and achieving full table programmability are presented. According to the proposed codeword grouping and symbol memory mapping, both group searching and encoding/decoding procedures are completed by applying numerical properties and arithmetic operations to codewords and symbol addresses. By a novel symbol conversion, the memory requirement of the encoding process is reduced and the programmability of codewords and symbols is achieved. For MPEG applications, a 0.6-/[micro]m CMOS design that performs concurrent VLC codec processes is shown. This VLSI implementation occupies an area of 5.0 x 4.5 [mm.sup.2] with 110 k transistors and satisfies a coding table up to 256-entry 12-bit symbols and 16-bit codewords. In addition, both encoding and decoding throughputs of this design achieve 100 Msymbols/s at a 100-MHz clock rate. Therefore, the proposed VLC codec system is suitable for applications which require high operation throughput, such as HDTV, and simultaneous compression and decompression, such as videoconferencing. Index Terms--Group-based, HDTV, Huffman coding, VLC codec, VLC/VLD.