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Several new Rapid Single-Flux-Quantum (RSFQ) circuits for digital applications are presented. The circuits, which belong to the family of Josephson junction digital devices, were tested via numerical simulations and experimental measurements. The rate errors in these circuits were also evaluated. Results show that the RSFQ circuits have wide parameter margins, thereby, ensuring a very low probability of digital errors.

A planarization technique for the very-large-scale integration of Nb-based Jospehson junction circuits is presented. The technique incorporates resist etch-back planarization and plasma enhanced chemical vapor deposition dielectrics to achieve a smooth topology for the junctions. It was employed in the fabrication of direct current superconducting quantum interference devices. Results indicate that the proposed technique is very useful for the very-large-scale integration of digital Nb circuits.

A novel 16-transistor CMOS 1-bit full-adder cell is proposed. It uses the low-power designs of the XOR and XNOR gates [1], pass transistors, and transmission gates. The cell offers higher speed and lower power consumption than standard implementations of the 1-bit full-adder cell. Eliminating an inverter from the critical path accounts for its high speed, while reducing the number and magnitude of the cell capacitances, in addition to eliminating the short circuit power component, account for its low power consumption. Simulation results comparing the proposed cell to the standard implementations show its superiority. Different circuit structures and input patterns are used for simulation. Energy savings up to 30% are achieved. Index Terms--Binary addition, full adder, high speed, low power.