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A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25-[micro]m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 [micro]m x 400 [micro]m is composed of a charge-sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event-upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery-time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In comparison to previous generations of the ATLAS pixel chip, FE-I2 incorporates many new features such as embedded 'smart' decoupling capacitances, long-term overvoltage protection, linear regulators, a capacitance calibration charge-pump circuit, a power-on reset, and a leakage current monitoring circuit. Its predecessor (FE-I1) has been demonstrated to operate correctly after ionizing radiation doses exceeding 50 Mrad (Si[O.sub.2]). Special techniques employed for digital pick-up reduction are also described. Index Terms--Active bias distribution, hybrid pixel sensor, leakage current compensation, multichip module, shielding technique, threshold adjustment, time over threshold.

A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25-/[micro]m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10 000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new dc feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single-event upset have been implemented for threshold and recovery-time pixel-to-pixel matching purposes. Special attention has been paid to the power-supply rejection ratio to minimize sensitivity to pickup. The complete cell dissipates 30 [micro]W, occupies an area of 50 x 90 [micro][m.sup.2] and is operated with a single 1.6-V power supply. Measurements of two test chips are presented. Index Terms--CMOS analog integrated circuit, fixed sensor, leakage current compensation, threshold mismatch, time over threshold.

A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 x 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. Index Terms--ATLAS pixel, charge amplifier, column readout, deep submicron, pixel readout, radiation hard.

Results obtained with a (photon) counting pixel imaging chip connected to a silicon pixel sensor using the bump and flip-chip technology are presented. The performance of the chip electronics is characterized by an average equivalent noise charge (ENC) below 135 e and a threshold spread of less than 35 e after individual threshold adjust, both measured with a sensor attached. First results on the imaging performance are also reported.

High Energy Physics experiments under preparation at CERN (Geneva, Switzerland) with the future LHC (Large Hadron collider) require a fast, low noise, very rad-hard, mixed analog-digital microelectronics VLSI technology. Readout electronics designed using such a technology for the central parts of the LHC particle detectors must withstand more than 10 Mrad (Si[O.sub.2]) and [10.sup.14] neutrons/[cm.sup.2] over 10 years of operation. We present here recent results obtained with a new rad-hard analog-digital technology called [DMILL.sup.1] [1-8], which monolithically integrates NPN bipolar, CMOS and P-JFET transistors, and which has been specifically developed to fulfill the severe constraints of LHC detector readout circuits.

We describe transient effects induced by high energy protons in shift registers processed in a CMOS/thick SOI technology. Devices are tested in dynamic mode. The dependence of cross section on frequency, signal rise time, angle of incidence and proton energy is studied and interpreted.

We present experimental results from a fast charge amplifier and a wideband analog buffer processed in the DMILL BiCMOS-JFET radhard SOI technology and irradiated up to 4.5 X [10.sup.14] protons/[cm.sup.2]. In parallel, we have irradiated elementary transistors. These components were biased and electrical measurements were done 30 min after beam stop. By evaluating variations of main SPICE parameters, i. e., threshold voltage shift for CMOS and current gain variation for bipolar transistors, we have simulated the wideband analog buffer at different doses. These SPICE simulations are in good agreement with measured circuit degradations. The behavior of the charge amplifier is consistent with extraction of transconductance and pinch-off voltage shift of the PJFET.

We present here recent results obtained on a rad-hard mixed analog-digital technology currently under development, which integrates monolithically complementary MOS transistors (CMOS), complementary JFETs (CJFETs) and complementary bipolar transistors (C-bipolars). This technology is expected to fulfill the hard constraints of LHC detector electronics.

A large surface semiconductor photon counting pixel detector is being built. As a first step, this detector is optimized for X-ray crystallography. The aim is to provide a high dynamic range (> [10.sup.9]), high counting rate ([10.sup.7] ph/s per pixel), and fast image readout (3 ms). A full custom chip has been produced and tested, and results are presented. Prototypes of 6 [cm.sup.2] containing pixels of 330 x 330 [micro][m.sup.2] have been built together with a full fast readout system. These prototypes have been tested in the D2am beam line at the ESRF synchrotron (Grenoble, France) for photon energies between 10 and 24 KeV. For photon energies above 10 keV, the signal is separable from the noise. We give results on the efficiency as a0 function of the photon rate and the effect of the threshold on the efficiency in the region between the pixels. Furthermore, to demonstrate the large dynamic range, we made diffraction images. Index Terms--Crystallography, detector, instrumentation, pixels, X-rays.

Pixel detectors with a high granularity and a very large number of sensitive elements (cells) are a very recent development used for high precision particle detection. At the Large Hadron Collider LHC at CERN (Geneva) a pixel detector with 1.4 * [10.sup.8] individual pixel cells is developed for the ATLAS detector. The concept is a hybrid detector consisting of a pixel sensor connected to a pixel electronics chip by bump and flip chip technology in one-to-one cell correspondence. The development and prototype results of the pixel front end chip are presented together with the physical and technical requirements to be met at LHC. Lab measurements are reported.

For X-ray diffraction experiments, the required dynamic range is a challenge. The signal ranges usually over more than six orders of magnitude. To meet this requirement and to reduce the readout time with respect to the commonly used charge-coupled device camera, a dedicated hybrid pixel detector is under development. We have designed a new counting chip with pixel size of 330 [micro]m. The expected counting rate per pixel is [10.sup.7] ph/s, and a continuous readout with time stamping will allow a dynamic range for up to 4 x [10.sup.9] (16-bit counter in each pixel and 16-bit counter per pixel in the readout boards). This chip has been submitted for fabrication and is under test. First results of this chip will be presented. As a first step, a small detector (4 x 1.6 [cm.sup.2]) is being built, using a DELPHI (LEP/CERN) silicon array of diodes, which have good efficiency for collecting X-rays between 5 and 25 keV. After the electrical tests, the performance of this X-ray detector will be measured in the ESRF-D2AM beam line (Grenoble, France), scheduled for December 2000. If this prototype performs as expected, a large array (25 x 25 [cm.sup.2]) of such detectors could be built.