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Purpose: Au stud bump bonding technology is an effective means to realize heterogeneous integration of commercial chips in the 2.5D electronic packaging. The purpose of this paper is to study the long-term reliability of the Au stud bump treated by four different high temperature storage times (200°C for 0, 100, 200 and 300 h). Design/methodology/approach: The bonding strength and the fracture behavior are investigated by chip shear test. The experiment is further studied by microstructural characterization approaches such as scanning electron microscope, energy dispersive spectrometer and so on. Findings: It is recognized that there were mainly three typical fracture models during the chip shear test among all the Au stud bump samples treated by high temperature storage. For solder bump before aging, the fracture occurred at the interface between the Cu pad and the Au stud bump. As the aging time increased, the fracture mainly occurred inside the Au stud bump at 200°C for 100 and 200 h. When aging time increased to 300 h, it is found that the fracture transferred to the interface between the Au stud bump and the Al Pad. Originality/value: In addition, the bonding strength also changed with the high temperature storage time increasing. The bonding strength does not change linearly with the high temperature storage time increasing but decreases first and then increases. The investigation shows that the formation of the intermetallic compounds because of the reaction between the Au and Al atoms plays a key role on the bonding strength and fracture behavior variation. [ABSTRACT FROM AUTHOR]

This research focuses on developing high-fidelity experimental and numerical models to analyze microscale underfill dynamics and void formation in high-density flip-chip packaging. Three underfilling scenarios are investigated, namely, point type, I-shaped line type, and L-type line type. The point-type underfilling validates the numerical model against experimental results, while the I-shaped and L-type line-type underfilling explore grid independence, void formation, and critical parameters such as filling position, contact angle, and liquid viscosity. Results indicate that contact angle and viscosity significantly influence filling efficiency and interface evolution. A smaller contact angle accelerates the process, reducing interface jumping motions. Viscous effects are quantified, revealing dimensionless filling time convergence. The use of low-viscosity surrogate fluids enhances numerical simulation efficiency. Sub-bump-sized, bump-sized, and sup-bump-sized voids are observed, identifying three void formation scenarios representing different underfilling flow mechanisms. This study provides insight into microscale flip-chip underfill physics and establishes validated models for next-generation high-density flip-chip products. These models can be further refined and integrated into optimization tools for automated process design, contributing to improved assembly yield and reliability of emerging electronic packages through physics-based understanding and modeling. [ABSTRACT FROM AUTHOR]

Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency. [ABSTRACT FROM AUTHOR]

Laminate substrates in advanced IC packages serve as not only the principal heat dissipation pathway but also the critical component governing the thermomechanical performance of advanced packaging technologies. A solid and profound grasp of their thermomechanical properties is of crucial importance to better understand IC packages' thermomechanical behavior. This study attempts to introduce a subregion homogenization modeling framework for effectively and efficiently modeling and characterizing the equivalent thermomechanical behavior of large-scale and high-density laminate substrates comprising the non-uniform distribution and non-unidirectional orientation of tiny metal traces. This framework incorporates subregion modeling, trace mapping and modeling, and finite element analysis (FEA)-based effective modeling. In addition, the laminates are macroscopically described as elastic orthotropic or elastic anisotropic material. This framework is first validated with simple uniaxial tensile and thermomechanical test simulations, and the calculation results associated with these two effective material models are compared with each other, as well as with those of two existing mixture models, and direct the detailed FEA. This framework is further tested on the prediction of the process-induced warpage of a flip chip chip-scale package, and the results are compared against the measurement data and the results of the whole-domain modeling-based effective approach and two existing mixture models. [ABSTRACT FROM AUTHOR]

The integrity of solder joints of components in an electronic device is critical to the device reliability. The miniaturisation trend in the development of electronic products has continued to challenge the shear strength of the solder joints in these devices and necessitates implementation of optimal reflow profiles to achieve maximum joint strength. This study proposes an optimal parameter combination of reflow profile factors which demonstrate potential for delivering maximum shear strength of solder joints. The Taguchi design of experiment (DoE) is employed to generate eight orthogonal array designs of L24 reflow profiles. The factors/parameters investigated are preheat gradient, time above liquidus (TAL), peak temperature and cooling rate. Three test vehicles of varying solder joint sizes are made from R1206, R0805 and R0603 resistors. Reflow profile number 3 constituting 1.2°C/s preheat, 45 s TAL, 245°C peak temperature and 60% cooling rate is optimal because it yielded joints with the highest strength and ca. 4 µm intermetallic compound thickness. The solder joint shear strength decreased with a decrease in the size of the lead-free joint irrespective of the reflow profile implemented. These results will be useful for electronic packaging and reliability engineers faced with challenges of improving device operational mechanical performance in the continuing trend of product miniaturisation. [ABSTRACT FROM AUTHOR]

In this study, the effects of a hybrid filler composed of zero-dimensional spherical AlN particles and two-dimensional BN flakes on the thermal conductivity of epoxy resin were studied. The thermal conductivity (TC) of the pristine epoxy matrix (EP) was 0.22 W/(m K), while the composite showed the TC of 10.18 W/(m K) at the 75 wt% AlN–BN hybrid filler loading, which is approximately a 46-fold increase. Moreover, various essential application properties were examined, such as the viscosity, cooling rate, coefficient of thermal expansion (CTE), morphology, and electrical properties. In particular, the AlN–BN/EP composite showed higher thermal stability and lower CTE (22.56 ppm/°C) than pure epoxy. Overall, the demonstrated outstanding thermal performance is appropriate for the production of electronic packaging materials, including next-generation flip-chip underfills. [ABSTRACT FROM AUTHOR]

In this paper a three-dimensional model of a novel electronic package has been developed using Finite element analysis to evaluate the shear load, tensile, bending and thermal stresses. Simulations of a complete flexible flip chip electronic packaging method are performed to minimize stresses on the packaged electronic device to improve robustness and reliability. Three component under-fill adhesives (Loctite 4860, Loctite 480 and Loctite 4902) and three circuit substrate materials (Kapton, Mylar and PEEK) are compared and the optimal thickness of each is found by shear load, tensile load, bending test and thermal expansion simulations. A fixed die size of 3.5 mm × 8 mm × 0.53 mm has been simulated and evaluated experimentally under shear and bending load. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. The Kapton substrate together with the Loctite 4902 adhesive were identified as the optimum in the simulation. The simulation of under-fill adhesive and substrate thickness identified an optimum configuration of a 0.045–0.052 mm thick substrate layer and a 0.042–0.045 mm thickness of the Loctite 4902 adhesive. The bending simulation has also been used to determine the neutral axis of the encapsulated electronic package in this paper, thus identifying the optimal material and thickness for the encapsulation layer of the package. [ABSTRACT FROM AUTHOR]

In order to control the interfacial intermetallics of the commonly used soldering joint in the electronics packaging products, copper and nickel-plated copper were selected as the substrates, SAC305 was selected as the solder, and a series of experiments were conducted. The pure copper was plated with nickel and then the nickel-plated copper substrate was heat-treated before reflow soldering. Effects of substrate heat treatment on reflow soldering and aging of the soldered joints were studied. The results show that the heat treatment of nickel-plated copper substrate before reflow soldering can enhance the adhesion between the substrate and the plated coating and it can inhibit the growth of interfacial intermetallic compound (IMC). In the aging process, the IMC layer thickness of the soldered joint without heat treatment on the substrate before reflow is thicker than that of the soldered joint with heat treatment before reflow. The IMC growth rate of the interfacial layer of the soldered joint without heat treatment on the substrate before reflow is 5.854 × 10–17 m2 s−1; the IMC growth rate of the interfacial layer of the soldered joint with the substrate heat-treated before reflow soldering is 3.193 × 10–17 m2 s−1. In the shear test, the shear strength of the solder joints with heat treatment on the substrate before reflow soldering is higher than that of the solder joints without heat treatment before reflow soldering. [ABSTRACT FROM AUTHOR]

Electronic devices need to work at high temperature in some fields for a long time, peculiarly step soldering technology, primary packaging and flip–chip connections, etc., along with the application of electronic products more and more widely. These phenomena promote the further development of high-temperature solders. Because of the high melting temperatures of Sn-Ag and Sn-Sb, they are suitable for high-temperature fields such as automotive electronics and avionics. In this review, the influences of trace elements and nanoparticles on microstructure, intermetallic components (IMC) growth, mechanical properties, wettability, melting behavior, and creep behavior of Sn-Ag and Sn-Sb solders have been summarized systematically. It was found that the addition of trace elements or nanoparticles into solders to be beneficial in improving the performance of Sn-Ag and Sn-Sb solders. Besides, the melting behavior of the solder at high temperatures can be further improved if Sn-Ag and Sn-Sb are used better as high-temperature solders. [ABSTRACT FROM AUTHOR]

SnBi lead-free solder is widely applied in the field of low-temperature soldering due to its excellent creep resistance, relatively low melting point (139 °C) and cost. However, the frangibility and poor ductility of the SnBi low-temperature solder limits its application in the field of electronic packaging. In this paper, the research progress and development direction of SnBi low-temperature lead-free solder are discussed. To promote the application of SnBi solder, the melting characteristics, wettability, microstructure, tensile properties, shear properties, creep properties and interfacial reaction of SnBi solder are analyzed and introduced systematically. It provides an important reference of understanding the current development of SnBi solders. [ABSTRACT FROM AUTHOR]

The demand for miniaturised electronic devices has led to various challenges in microelectronic industries. One of the challenge is the removal of fans in some applications, which has led to increased heat retention, thereby causing overheating. In the assembly of electronic devices, thermal interface materials (TIMs) can be used for bonding the surface between the flip chip and a heat sink base or heat spreader. Lead-free solder (Sn-Ag-Cu) alloys are becoming more popular as TIMs in electronic assembly. Therefore, these lead-free solders could fail during operation at elevated temperatures over a period of time. The reliability of lead-free TIMs is vital in sustaining the life span of an electronic device. Three Sn-Ag-Cu (SAC) solders were considered for this investigation, namely, SAC305, SAC105, and SAC396. An ANSYS design modeller was used in the design and analysis of the microelectronic application investigated. Temperature loads ranging between 100°C and 200°C were applied over a period of time during the simulation of the electronic package. The findings from the research suggested that the SAC305 solder TIMs will outperform SAC105 and SAC396 during operation. This is because SAC305 can accommodate more stress, while the strain rate is low compared to SAC105 and SAC396. In addition, the fatigue life of SAC305 was higher than that of SAC105 and SAC396 in the different temperature ranges investigated. Therefore, SAC305 is recommended as a better thermal interface material compared to SAC105 and SAC396. [ABSTRACT FROM AUTHOR]

Void formation is a critical reliability concern for solder joints in electronic packaging. The control of microstructures and the quantity of impurities in Cu electroplated films significantly affect void formation at the joint interface, but studies investigating these factors are rare. In this study, three Cu films (denoted as A, B, and C) are fabricated using an electroplating process. The Cu A film has a faceted grain texture embedded with twin boundaries, while Cu B and C films have similar columnar textures. After thermal aging at 200 °C for 1000 h, the SAC 305 (Sn-3.0Ag-0.5Cu) solder joints with Cu A and B films exhibit robust interfacial structures without voids. However, microstructural collapse is observed in the solder joint of SAC 305/Cu C, where many crevices are formed parallel to the interface. Based on the microanalysis, the concentration of impurities is higher in Cu C than in Cu A and B. Moreover, discrete voids rather than continuous crevices are present in the SAC305/Cu C system when the impurity concentration in Cu C is reduced. The findings demonstrate that impurity control in Cu electroplated film is critical for the control of void/crevice formation in electronic solder joints. [ABSTRACT FROM AUTHOR]

Nanosilver paste, an interconnect solder, is a common choice in the electronic packaging industry; however, higher sintering temperatures and lower sintering strength limit its application. At present, core–shell nanoslurry has been studied and applied to chip interconnection. Based on the mechanism of heterogeneous flocculation, we have developed a new nanosilver wrapped tin paste (Sn@Ag paste), and according to the decomposition temperature of the organic dispersant in the slurry, a corresponding sintering process with a temperature of 300 °C was developed. The Sn@Ag core–shell structure makes Sn have good dispersibility and oxidation resistance, and the sintered product of the slurry is a mixture of a solid solution of Ag and an Ag3Sn phase. Among them, the hard and brittle phase Ag3Sn acts as a dispersion strengthening effect in the Ag matrix phase, and the solid solution of Ag acts as a replacement solid solution strengthening. With the increase of doping Sn content, the sintering strength is significantly improved. When the Sn content is 5%, the joint shear strength reaches the highest value of 55 Mpa, which is higher than the pure nanosilver paste by 10 Mpa. This new nanosilver wrapped tin paste technology has the characteristics of low-temperature sintering and high-temperature service. [ABSTRACT FROM AUTHOR]

The mass reflow (MR) process is widely used in electronic packaging interconnection. However, the conventional MR process can cause thermal damage to components and requires a long process time. The laser-assisted bonding (LAB) process is considered as an alternative soldering process for overcoming these limitations due to its extremely fast process time and high thermal selectivity. The LAB process causes low thermal damage; hence, it can be used to fabricate flexible and stretchable applications. This study investigates the mechanical properties, microstructural variation, and intermetallic reaction between the SAC 305 solder and Cu electrodes. The mechanical properties are investigated using shear tests, while the microstructure is analyzed using scanning electron microscopy and X-ray scans. Furthermore, the reliability of the LAB- and MR-produced SAC 305 solders is assessed using a high-temperature storage test. As a result, the intermetallic compound layer is found to be considerably thinner, and the volume of voids in the solder matrix is lower in the LAB-produced solder than that in the MR-produced solder. The mechanical properties of the LAB-produced solders are enhanced by these microstructural advantages. [ABSTRACT FROM AUTHOR]

Low temperature solder (In-based, Sn-Bi, Sn-Zn) has great advantages in aerospace and through-hole technology assemblies in IBM mainframe due to its unique low temperature characteristics. The review evaluates the effects of alloying elements, rare earth elements and nanoparticles on the wettability, microstructure, mechanical properties and oxidation resistance of the low-temperature solders. [ABSTRACT FROM AUTHOR]

We studied the evolution of the Cu6Sn5 and Cu3Sn intermetallic compounds under large thermal gradients for assisted directional solidification in Cu/Sn/Cu micro solder units for fast bonding in 3-D IC packaging. Thermomigration-enhanced growth and dissolution of the phasesare observed and tracked using a CALPHAD-reinforced multiphase-field model that accounts for the thermodynamics and kinetics of the Cu(Sn) reacting system. The results show that the process of bonding follows a reaction-controlled growth regime ($n{\sim }1$) during thermal gradient bonding, proceeding faster than isothermal conditions. In addition, the asymmetric phase evolution, i.e., simultaneous growth in hot side and dissolution in the cold side of the interconnect, is modeled. The developed model can be used for the proactive control of the complex heat treatment processes for the design of multicomponent low-volume solder interconnects in electronic packaging. [ABSTRACT FROM AUTHOR]

Residual deformation evaluation of underfill (UF) materials in flip chips is crucial to improve the reliability of electronic packages. In this study, we propose to evaluate the residual thermal strain distributions using an inverse method based on the sampling moiré technique. Even if a grid pattern is fabricated on the specimen at room temperature, the residual strain distributions at an arbitrary temperature relative to the specimen formation temperature can be successfully calculated. The residual strain distributions relative to the free contraction state at an arbitrary temperature can also be measured when the coefficient of thermal expansion is available. A thermal chamber for flip chips was designed under a laser scanning microscope. Using the proposed method, the normal, shear and principal internal strain distributions and deformation characteristics of two kinds of UFs in flip chips were investigated relative to 150 °C. The strains of the UF with low glass transition temperature (UF-A) concentrate near the die material, especially at the die corner, while the strain concentration of the underfill with high glass transition temperature (UF-B) mainly occurs at the die corner and the buffer layer. The maximum principal strain of UF-A is greater than that of UF-B around the die corner. The residual maximum principal strain distributions relative to the free contraction state at 25 °C were compared with the simulation results by the finite element method. The residual strain distribution trends from experiments are consistent with those from simulations. [ABSTRACT FROM AUTHOR]

With the development of electronical technology and the construction of the fifth-generation cellular networks, electronic devices with higher integrated level and power are widely applied. Hence, greater demands are being placed on electronic packaging materials. High-Pb solder alloys were widely used for low- and medium-temperature soldering for the past decades but have been prohibited due to toxicity. Au-based solder alloys with proper melting and mechanical properties show great potential to replace high-Pb solder alloys and are being emphasized recently. But in comparison with Pb-containing solder alloys, the investigation on novel Au-based solder alloys is quite insufficient, and their performance and reliability are still unclear. In this paper, the recent research studies on Au-based solder alloys with low temperature and medium temperature were reviewed and their microstructure, mechanical performance, and reliability were introduced and analyzed. Moreover, the novel processing technologies of Au-based solder alloys were discussed and compared. [ABSTRACT FROM AUTHOR]

Electromigration in flip chip solder joints under extra high current density (4.5×104 A/cm2) is studied. At such a high current density level, due to Joule heating, the chip temperature is strongly coupled to the applied current density. Accordingly, it is highly desirable to have the capability to decouple the chip temperature and the current density. Two experimental setups were used in this study, one with a cooling module to keep the chip temperature constant and the other one without a cooling module. Without the cooling module, the temperature increased rapidly with the applied current. When the current density reached 4.5×104 A/cm2, a rapid failure caused by excessive Joule heating was observed only after 10 min of current stressing. With the cooling module attached, the joint exhibited a much longer life (935 h) under 4.5×104 A/cm2. It was successfully demonstrated that the cooling module was able to decouple the applied current density and the chip temperature. [ABSTRACT FROM AUTHOR]

Semiconductor devices are commonly encapsulated with Epoxy-based Moulding Compounds (EMC) to form an electronic package. EMC typically occupies a large volume within a package, and thus, governs its thermomechanical behaviour. When exposed to high temperatures (150 °C and above), electronic packages predominantly show oxidation of the outer layer of EMC. Oxidized EMC exhibits notably different material properties, resulting in a modified deformation pattern of a thermally aged package under varying thermal loads. As the oxidation layer grows in thickness, its mechanical properties also evolve, indicating distinct phases of the oxidized material at different stages of thermal ageing. Reflecting these changes (i.e. , the current state of degradation) into a Finite Element (FE) model-based analysis can provide better insights into failure prediction and component reliability. It requires updating the geometry and material behaviour as a function of ageing. This paper presents a systematic procedure to build a continuously updated physics-based Digital Twin of a thermally aged flip-chip package that can represent intermediate oxidation stages. First, experimental measurements are carried out to quantify the growth of the oxidation thickness at 150 °C and a diffusion-dominant mathematical model is proposed. Then, an accurate geometry of the test package is prepared with a parametric outer layer from all exposed sides of EMC to represent the oxidized layer at different stages of thermal ageing. Next, the experimental characterization of a few partially oxidized EMC specimens is done, and analytical methods are utilized to extract the thermomechanical properties of the oxidized EMC at different stages of ageing. Experimental warpage data of aged test packages are utilized to verify the defined material-model parameters that represent curing shrinkage, thermal expansion, glass transition, and corresponding elasticity moduli of the oxidized EMC at select stages of ageing. Then, a workflow to establish continuity in the material model is presented. Finally, the developed Digital Twin is utilized for an FE analysis to study the change in the trend of out-of-plane package deformations as a function of several stages of EMC oxidation. [Display omitted] • Three-step modelling procedure to represent thermo-oxidative changes in EMC. • Six-parameter material behavioural model of EMC at different stages of oxidation. • Thermal ageing enlarges package deformation (warpage) with a temperature-delay. [ABSTRACT FROM AUTHOR]

For electronic packaging engineers in the high-reliability sectors, such as aerospace, defense, oil & gas, etc., the use of commercial off-the-shelf components offers significant advantages due to their high availability, fast delivery time, and low cost. However, these components pose significant reliability challenges due to the risks associated with tin whisker formation and uncertainty on the long-term reliability of lead-free solders. For addressing these risks, the hot solder dip process is used to refinish the package by replacing lead-free solder finishes with lead-based finishes to meet the stringent packaging and assembly requirements for these sectors, which are exempt from restriction of hazardous substances (RoHS) legislation. But the hot solder dip process is an extra process that exposes the package to an additional thermal load, which will result in thermomechanical stresses that need to be properly understood and controlled. For addressing this challenge, a multidisciplinary methodology combining thermomechanical models with “dip-to-destroy” experiments and scanning acoustic microscopy has been developed to identify the risk of package material delamination for a number of package designs. Results show that the developed models can predict delamination risks for a range of imposed thermal gradients. Electronic package designs with a direct heat path from dipped terminations to the internals of the package show a higher risk of overstress-induced delamination, and this failure is generally driven by the high-temperature excursion above the glass transition point of the molding compound. The novelty and significance of these findings is that the derived methodology can be used by electronic packaging designers to optimize the thermal parameters of the hot-solder-dip process so that subsequent refinished packages can meet the stringent high-reliability requirements for these sectors. [ABSTRACT FROM AUTHOR]

Fine-pitch flex-on-flex (FOF) assembly has been introduced for various electronic packaging applications because electronic products require higher functionality, flexibility, and I/O density. In this article, novel polyvinylidene difluoride (PVDF) anchoring polymer layer (APL) solder anisotropic conductive films (ACFs) were investigated for fine-pitch FOF applications. The capture rates of conductive particles and the insulation rates between neighboring electrodes have been significantly enhanced using PVDF APL solder ACFs as a result of suppressing the movement of conductive particles by the high tensile strength of the PVDF APL layer. For good solder wetting on electrodes, flux activators were added into the PVDF APL layer to remove the solder oxide layer. However, the tensile strength of the PVDF layer decreased as the flux activator content in the APL increased. The capture rates of conductive particles decreased as more flux activators were added because of the lower tensile strength of PVDF. Furthermore, optimized flux activator content in ACFs with 0.5 wt% in the APL and 2-wt% flux activators were also added in non- conductive films (NCFs) to obtain good solder wetting. Using the optimized APL solder ACFs, excellent contact resistances and insulation resistances were obtained before and after a pressure cooker test (PCT) and 85 °C/85% relative humidity (RH) reliability tests. As a conclusion, the PVDF APL solder ACF assembly can provide an excellent interconnect solution for fine-pitch FOF assemblies used for portable electronic product applications. [ABSTRACT FROM AUTHOR]

Eutectic 63Sn-37Pb solder is a typical viscoplastic material widely used in aerospace applications. In order to benchmark the mechanical reliability of electronic packaging structures in harsh environments, this study focused on the constitutive behavior of the solder. A unified creep-plasticity constitutive model is proposed with an enriched flow rule to satisfactorily describe the plastic and hardening stages. The strain rate range of 10-4 and 10-2 s-1 and the temperature range of -55 and 125°C are covered by a series of comprehensive uniaxial tensile experiments. Moreover, the experimental results are analyzed to elucidate the underlying mechanism of the calibrated parameters. It is found that the drag strength increases with temperature, while its slope is reduced with the strain rate. The short range of back stress is closely associated with temperature to influence the hardening slope of the stress–strain relationships. The value of hardening exponent is sensitive to strain rate and thus determined to be 0.52 and 2.72 for the strain rate greater and less than 2·10-4 s-1, respectively. The strain rate and temperature ranges in this study are capable of covering the temperature cycling tests for reliability qualification of electronic devices. Thus, the proposed enhancement of the unified creep-plasticity constitutive model facilitates the finite element simulations of packaging structures under temperature cycling conditions. This framework of the proposed constitutive model is readily extended to other types of viscoplastic solders within wide strain rate and temperature ranges. [ABSTRACT FROM AUTHOR]

In recent years, Moore's law had a remarkable effect on predicting the development of semiconductor technology. As the size of devices shrinks to micro scale or nano scale, Intel's newest 10-nm logic technology is scheduled to start product shipments before the end of 2017. Moore's law will not die out, as the research scale reaches the atomic scale, "new devices" and new interconnection methods are urgently needed. In this paper, based on emerging interconnection requirement, the contribution to the advanced electronic packaging containing novel nano-materials, such as the carbon nanotubes, nanoparticles sintering, interconnection of nano-solder, nano-silver and surface plasma nano-welding are discussed. For the next 5–10 years, two new types of interconnect solutions are gaining attentions: solder joint alternatives and Cu electrode alternatives. The former uses new materials such as graphene, carbon nanotubes and nanowires to replace traditional solder joints. The latter uses optical media to replace the traditional Cu metal. In general, advanced materials will make more and more outstanding contributions in the development of electronic packaging in the next 10–20 years. [ABSTRACT FROM AUTHOR]

[Display omitted] • Solderless Cu-Cu direct bonding was achieved by Cu micro-cone without CMP at 250 ℃. • The interlocking bonding interface and 116.4 MPa shear strength were achieved. • High stress and low yield stress led by micro-cone promote plastic deformation. In the post-Moore's era, Cu-Cu direct bonding has garnered significant attention as a promising alternative to solder joints for chip interconnection in advanced electronic packaging technology. Its advantages lie in reduced process restrictions and steps, as well as lower bonding temperature, which align with the demands for low cost and high compatibility. In this study, (1 1 0)-oriented micro-cones Cu was fabricated via template-free pulse electrodeposition, enabling solderless Cu-Cu direct bonding at 250 ℃ under three distinct bonding pressures without chemical mechanical polishing (CMP). The contact bonding area and shear strength gradually increased corresponding to the applied bonding pressure. Seamless bonding interface was achieved under high bonding pressure, leading to high shear strength of 116.4 MPa for Cu-Cu bonding joints. The obtuse polygon pyramid micro-cones, characterized by an enlarging cross-sectional area from apex to base, coupled with inherent mechanical properties, induce high applied stress at micro-cone's tip and a low yield stress, facilitating the initiation and propagation of plastic deformation during the bonding process. This study has demonstrated the feasibility of utilizing the micro-cones Cu for low-temperature bonding without CMP treatment, offering valuable insights into the advanced interconnection technologies. [ABSTRACT FROM AUTHOR]

As a result of the ban of lead from solder joints, many lead-free solder joints were developed. Most of the electronic equipment is subjected to random vibration. This study develops an analysis methodology based on finite element analysis and vibration tests to predict the failure and fatigue life of the electronic package soldered using Sn-1Cu-1Ni-1Ag under random vibration. A specially designed printed circuit board having ball grid array packages soldered is used in the study. Finite element model is developed in ANSYS and modal analysis was done. The finite element results were validated with experiments (impact test). Random vibration analysis was also done. These results were validated with random vibration experiments. Using the finite element results, it was predicted that the corner solder joints will fail first. It was observed in the random vibration experiment that corner solder joint failed first and the maximum stress generated was 12.8 MPa. Thus, Sn-1Cu-1Ni-1Ag is a promising lead-free solder joint alloy under random vibration combining with its mechanical properties. [ABSTRACT FROM AUTHOR]

Flip chip technology has been widely used in IC packaging, and the combination of flip chip technology and solder joint interconnection technology has been utilized in the manufacturing of electronic devices universally. As the development of flip chip towards high density and ultra-fine pitch, the inspection of flip chips is confronted with great challenges. In this paper, we developed an intelligent system used for the detection of flip chips based on vibration. Thirty-four features including 18 time domain features and 16 frequency domain features were extracted from the raw vibration data. The support vector machine was employed to implement the recognition and classification of flip chips. In order to improve the classification accuracy of SVM, cross validation (CV) and genetic algorithm (GA) were utilized to optimize the parameters of SVM respectively. SVM, CV-SVM and GA-SVM were applied to classification separately and the results were obtained. By comparison, GA-SVM can recognize and classify the flip chips rapidly with high accuracy. Thus, GA-SVM is effective for the defect inspection of flip chips. [ABSTRACT FROM AUTHOR]

3-D chip-stacking packages and 3-D through silicon via (TSV) vertical interconnection are popular flip-chip assembly methods. Cu-pillar/SnAg micro bumps have usually been used for vertical interconnections in the 3-D TSV chip stacking. These vertical interconnections are fabricated using a thermocompression bonding method with nonconductive films (NCFs). The fabrication heat and pressure lead to molten solder wetting the pad. However, the deformed molten solder on the sidewall of the Cu-pillar results in an increase in solder and Cu-pillar contact interfaces. As a result, more Sn is consumed and Kirkendall voids occur at the solder joint. Novel double-layer NCFs (D-NCFs) can solve the problem of solder wetting the sidewall of the Cu-pillar. D-NCFs are two NCF layers, consisting of a fast-curing top NCF layer and a slower-curing bottom NCF layer. The top NCF layer is designed to have a curing onset temperature below the melting temperature of the solder, to prevent the molten solder wetting the Cu-pillar sidewall. The bottom NCF layer, which has a slower curing property and flux ability, helps the molten solder wet the pads. In this paper, D-NCFs were investigated for the wafer-level (WL) processing of 40- \mu \textm fine-pitch Cu-pillar/SnAg micro bump chip assemblies. The D-NCFs properties were first adjusted for WL capability, and then bonding conditions were optimized in terms of solder wetting on the Cu-pillar and electrical interconnection. As a result, the D-NCFs were found to significantly increase the amount of Sn solder remaining between the Cu-pillar/SnAg/Cu interconnection, and also to decrease Sn consumption. [ABSTRACT FROM AUTHOR]

As a heterogeneous integration technology, chiplet-based design technology integrates multiple heterogeneous dies of different functional circuit blocks into a single chip by using advanced packaging techniques, such as advanced packaging technology, advanced components, advanced ICs, advanced test carriers and advanced architectures. In this issue, we collected 12 papers and covered the flip-chip technology, flex-on-board interconnection, double-sided silicon vias, Au-coated Ag alloy, W-band antenna, hybrid bonding, system-in-packaging integration, etc. It covers a variety scopes: system-in-package; fan-in/fan-out wafer level package; panel level chip-scale package; 2D, 2.1D and 2.3D integration; 2.5D integration; 3D IC integration; and chiplet heterogeneous integration. [Extracted from the article]

Flip-chip package reliability is greatly improved by encapsulating the solder interconnections between a polymeric encapsulant or underfill. However, thermo-mechanical stresses within such packages often lead to failures initiating in the vicinity of chip and underfill interface. In this study, we present experimental results geared towards measuring and understanding such failure mechanisms. We provide the bulk fracture toughness of the underfill material and interfacial fracture toughness between the underfill material and the silicon die. The bulk and interfacial fracture toughness measurements are performed as a function of temperature. We use the single edge notch bending test to calculate the bulk fracture toughness of the underfill and to measure the interfacial fracture toughness, we use a novel technique referred to as the wedge delamination method. The wedge delamination method provides substantial advantage in measuring the interfacial fracture toughness for brittle materials over traditional methods. Using the wedge delamination method we compare the fracture strength between the underfill and silicon at the front-face and side-wall interfaces. Additionally, the influence of dicing technique on fracture toughness is also investigated. [ABSTRACT FROM AUTHOR]

In the microelectronics industry the flip-chip (FC) technology is broadly used to enhance the packaging density. However, the small size and the unique geometry of the FC solder joints induce the electromigration (EM) reliability issue. In this study, a pair of lead-free solder joints (SAC1205) was EM tested by a current of 7.5 × 10 3 A/cm 2 . During the tests, X-ray laminography was applied to observe the microstructure evolution in-situ . Laminography enables the non-destructive observation of the bump microstructure and allows for a quantitative three-dimensional (3D) analysis. After EM testing for 650 h, a new EM failure mechanism was found, differing from the two well-known models, the pancake void propagation and the under-bump-metallization dissolution. Here, a few pre-existing small voids grew and simultaneously many new voids formed and grew over the entire EM testing period. Most of the nucleating voids were distributed in the current crowding region, a few also located in the low-current-density region. As the testing time increased, voids increasingly coalesced with each other, forming a porous network which occupied a large part of the interface area and caused the EM failure. A finite-element (FE) method was then applied to analyze the interplay between the microstructure evolution and current density redistribution. A series of 3D FE models was built based on the laminography images for the different testing stages. The current density distribution from the FE analysis indicates that the formation of discrete voids did not affect the global current density distribution until a major coalescence of the voids occurred. The relieving of the global current crowding in the pancake void model was not found in this new EM failure mechanism. It was the local current crowding around individual void found in the new mechanism that is held responsible for the EM retardation. [ABSTRACT FROM AUTHOR]

The structural integrity on low-k layers is a major reliability concern on three-dimensional packaging technology. The low-k material used in dies has a reduced stiffness and adhesion strength to the barrier materials, which makes the back-end-of-line (BEOL) structure much more vulnerable to the externally applied thermal stress during the flip-chip packaging. This thermal stress can cause a serious impact on the reliability and yield of electronic components, and hence the stress optimization is required. This paper aims to create an equivalent thermal stress model to evaluate the stress conditions in different low-k layers generated during the assembly. The model has only one sub-model and is verified by the flip-chip assembly of a 40 nm technology node chip. It is shown that this thermal stress model has the potential to predict the stress variation tendency in the different BEOL layers and hence can be used for the chip packaging interaction study. [ABSTRACT FROM AUTHOR]

Intel fourth-generation and fifth-generation Core microprocessors are powered by high-frequency integrated switching voltage regulators. The inductors required to implement these regulators are constructed using the routing layers of conventional organic flip chip packaging. This paper provides an overview of the construction of these inductors including representative results from production packages. Measured inductors reported in this paper span from 1 to 6.7 nH under 2.4 mm2 and achieve $Q$ of up to 24 at 140 MHz (the switching frequency). [ABSTRACT FROM AUTHOR]

Chip picking-up with vacuum sorption is a critical technology in flip-chip packaging for separating chip intactly from donor adhesive tape. With increasing length/thickness ratio of chips, the incomplete separation affects the success rate of this process, even leads to the failure of chips. Here, we present a theoretical model with a bisection algorithm to calculate the effective size of tape that contributes to the crack growth, and introduce an energy release rate and pick-up force to evaluate the ability of thin chip picking-up. The finite-element method with a virtual crack-closure technique is constructed to validate the established process model. The effects of the type of pick-up head, length of chip, thickness, and material of tape on chip picking-up process are also revealed to improve the ability to propagate a crack in the adhesive layer. Furthermore, the crack propagation in the adhesive layer with increasing pick-up displacement is predicted to determine the critical value of the thin chip complete separation from compliant tape. These results suggest that the thinner and more compliant tape should be adopted in the chip picking-up process. [ABSTRACT FROM PUBLISHER]

This paper deals with the study of technologies for flip-chip assembly of CMOS integrated power converters on standard FR4 organic substrates. Tests for the characterization of commercially available technologies for microassemblies, such as anisotropic adhesive bonding, thermocompression bonding, thermosonic/ultrasonic bonding, and solder bonding, are carried out. The aim of this paper is to determine the most suitable flip-chip bonding technology for power CMOS circuits with more than 50 pads. First, the coupled design of the CMOS chip and the corresponding substrate dedicated to low-power microconversion (10 W) is presented. It is shown that the parasitic resistances and inductances of the interconnections increase the conduction and switching losses of the device. This leads to a temperature rise, which can limit the operating ratings of the circuit. The experimental results are provided to evaluate each technology for flip-chip assembly. [ABSTRACT FROM PUBLISHER]

Flip-chip technology has been widely accepted as a solution for electronic packaging of high-pin-count devices. Due to the demand for smaller and thinner package dimensions, coreless build-up substrates will be used in industry to carry the die by solder bumps due to the advantages of shorter transmission route and lower inductance and thermal resistance. However, coefficient of thermal expansion (CTE) mismatch between the Cu trace and the laminate often causes the coreless substrate to warp, which leads to failures such as nonwetted solder bumps and interfacial cracking during assembly and reliability tests. In a previous study, assembly of a six-layer polyimide-based coreless flip-chip package was achieved by a 17 mm × 17 mm die with 4355 Sn-37Pb solder bumps, an amide-based underfill, and 1521 Sn-3.0Ag-0.5Cu solder balls. For determination of its board-level reliability characteristics, the component was mounted on a printed circuit board (PCB) using a conventional surface mount technology, and 10 test vehicles were assembled for assessment of their reliability under a temperature cycling environment. The experimental results show that the characteristic life of the PCB assembly exceeded 1500 cycles and that failure resulted from fracture of the outermost solder balls on the substrate side. This was different from the failure mode of die cracking when the package experienced hundreds of temperature cycles at the component level because the rigid PCB, through solder balls, moderated the deformation of the coreless flip-chip package. Hence, the concentrated bending stress at the die edge region was lowered. Finally, the local CTE mismatch between the stiffener and the PCB dominated the fatigue fracture of the outermost solder balls to become the main failure mode. [ABSTRACT FROM AUTHOR]

Continuous decrease in the transistor technology sizes has enabled much denser packaging of electronic components on chips, which has resulted in integrated circuits with lower costs and area. However, it has also given rise to new issues and challenges in the process of integrated circuit design, including higher vulnerability to soft errors. Modular hardware redundancy is a popular method for improving the reliability of a system against errors at a cost of increasing area and energy consumption. Voltage scaling methods can be employed to tackle high energy costs; however, this also negatively affects the circuit's reliability and performance. Therefore, designing circuits with all these conflicting parameters is a very challenging task. In this study, we propose integer linear programming (ILP)-based high-level synthesis (HLS) methods to optimize both reliability and/or energy under the area and latency constraints. Our models employ full and partial duplication to improve the system reliability as long as the area constraint permits. They also utilize voltage islands as the energy reduction method of choice. What makes this problem even more interesting and complex is the fact that we use different versions of the same resources that have different area, latency, reliability, and energy values. Although this affects the execution time of the proposed methods, it also gives us more design options. We compared and showed the effectiveness of our methods against a genetic algorithm-based one on several HLS benchmarks. The ILP-based methods return the optimum results most of the time under the given time limits. • We propose ILP-based HLS methods to optimize reliability and energy in ASIC design. • Our models employ full and partial duplication to improve the system reliability. • We use voltage islands as the energy reduction method of choice. • Different versions of the same resources are used to meet the constraints. [ABSTRACT FROM AUTHOR]

Demand for more interconnection joints between semiconductor devices can be realized with solder bump technology. Surface tension and density are usually material properties related factors that affect solder bump geometric shape. Therefore, to cope with this fast-changing microarchitecture design in semiconductor technology, a better understanding of the solder bump geometric shape is needed. This study used a static equilibrium force approach to integrate the surface tension and gravitational energy into the solder energy content. Surface Evolver software was used to perform calculations and deliver the final solder bump shape. Perfect agreement with less than 10 % comparison between previous studies and the current Surface Evolver results was found. According to statistical analysis using SPSS, the maximum width of solder shape is closely related to the surface tension. In contrast, the maximum standoff is highly correlated with the solder density. By changing the solder volume, the solder bump changes from standard flip-chip bump to Cu pillar bump with consistency in maximum width to maximum standoff height ratio of 1.5. This study shows that the bumping technology can produce various sizes of solder bumps to meet new electronic packaging requirements. [ABSTRACT FROM AUTHOR]