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A Dual-Edge-Triggered (DET) flip-flop (FF) that can reliably operate at low voltage is proposed in this paper. Unlike the conventional Single-Edge-Triggered (SET) flip-flops, DET-FFs can improve energy efficiency by latching input data at both clock edges. When combined with aggressive voltage scaling, significant efficiency improvement is expected. However, prior DET-FF designs were susceptible to Process, Voltage and Temperature (PVT) variations, limiting their operation at low voltage regimes. A fully static true-single-phase-clocked DET-FF is proposed to achieve reliable operation at voltages as low as a near-threshold regime. Instead of the two-phase or pulsed clocking scheme in conventional DET-FFs, a True-Single-Phase-Clocking (TSPC) scheme is adopted to overcome clock overlap issues and enable low-power operation. Fully static implementation also enables robust operation in a low voltage regime. The proposed DET-FF is designed in 28nm CMOS technology, and a comprehensive analysis including post-layout Monte Carlo simulation for wide PVT ranges is performed to validate the design approaches. Extensive analysis and comparison with prior-art DET-FFs confirmed that the proposed DET-FF can operate at the lowest voltage of 0.28 V for a temperature range of -40 °C to 120 °C while maintaining nearly-best energy efficiency and power-delay-product.

Negative differential resistance/transconductance (NDR/NDT) has been attracting significant attention as a key functionality in the development of multivalued logic (MVL) systems that can overcome the limits of conventional binary logic devices. A high peak-to-valley current ratio (PVCR) and more than double-peak transfer characteristics are required to achieve a stable MVL operation. In this study, an organic NDR (ONDR) device with double-peak transfer characteristics and a high peak-to-valley current ratio (PVCR;10

We present a discontinuous harvesting approach for switch capacitor dc–dc converters that enables ultralow-power energy harvesting. Smart sensor applications rely on ultralow-power energy harvesters to scavenge energy across a wide range of ambient power levels and charge the battery. Based on the key observation that energy source efficiency is higher than charge pump efficiency, we present a discontinuous harvesting technique that decouples the two efficiencies for a better tradeoff. By slowly accumulating charge on an input capacitor and then transferring it to a battery in burst mode, dc–dc converter switching and leakage losses can be optimally traded off with the loss incurred by nonideal maximum power point tracking operation. Harvester duty cycle is automatically modulated instead of charge pump operating frequency to match with the energy source input power level. The harvester uses a hybrid structure called a moving-sum charge pump for low startup energy upon a mode switch, an automatic conversion ratio modulator based on conduction loss optimization for fast conversion ratio increment, and a 40% end-to-end efficiency from 113 pW to 1.5 $\mu \text{W}$ with 20-pW minimum harvestable input power.

A two-way oxide rupture scheme in a transistor is proposed for area-efficient PUF implementation for low-cost IoT systems. Compared to a conventional one-way oxide rupture scheme, which requires a 4T unit cell structure, the proposed scheme allows a 2T unit cell structure, which enables up to 70% area reduction. A test chip is fabricated in 180 nm CMOS process to evaluate the effectiveness of the proposed scheme, confirming good randomness and uniqueness with small area overhead.

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

The nature of repetitive learning and oblivion of memory enables humans to effectively manage vast amounts of memory by prioritizing information for long-term storage. Inspired by the memorization process of the human brain, an artificial synaptic array is presented, which mimics the biological memorization process by replicating Ebbinghaus' forgetting curve. To construct the artificial synaptic array, signal-transmitting access transistors and artificial synaptic memory transistors are designed using indium-gallium-zinc-oxide and poly(3-hexylthiophene), respectively. To secure the desired performance of the access transistor in regulating the input signal to the synaptic transistor, the content of gallium in the access transistor is optimized. In addition, the operation voltage of the synaptic transistor is carefully selected to achieve memory-state efficiency. Repetitive learning characterizing Ebbinghaus' oblivion curves is realized using an artificial synaptic array with optimized conditions for both transistor components. This successfully demonstrates a biologically plausible memorization process. Furthermore, selective attention for information prioritization in the human brain is mimicked by selectively applying repetitive learning to a synaptic transistor with a high memory state. The demonstrated biologically plausible artificial synaptic array provides great scope for advancement in bioinspired electronics.

Wireless sensor nodes (WSNs) are essential elements for today’s structural health monitoring (SHM). As the design technology for WSNs evolves, there have been continuous efforts to address challenges for WSNs such as short lifetime, high power consumption, and bulky volume. Recent trends show energy harvesting becoming a popular solution for extending the lifetime of WSNs; even implementing energy-autonomous systems is an option. Smaller WSN form factors have been developed for volume-limited applications and sensor nodes as small as a few mm $^{3}$ were created with custom-designed integrated circuits (ICs). Custom IC-based sensor nodes enable energy-efficient implementation of WSNs for SHM. Ultralow power circuits with operation power on the order of nanowatts are introduced in this paper. Ultralow power energy harvesters, timers, wakeup receivers, sensing modalities, and microprocessors are expected to significantly extend sensor node lifetime or achieve sensor node operation with ambient energy harvesting.

This paper presents comprehensive analyses of power-performance tradeoffs in current-mode logic (CML)-based transmitters via equation-based optimization and provides practical design guidelines that can help achieving optimum power efficiency. An accurate equation-based optimization framework was developed for this purpose, and using this framework, key circuit-level design parameters were found with specific design specifications and process technologies. The proposed optimization framework can determine optimum clock edge-rate (i.e., ratio of rise/fall time to clock period) and inter-stage voltage swings that enable significant power savings without affecting performance. Various transmitter design tradeoffs were analyzed for 45-nm, 65-nm, and 90-nm technologies considering data rate, clock edge-rate, and inter-stage swing optimization. Based on the analysis results, we determined the most energy-efficient data rate that can be achieved with acceptable power overhead for each technology node. Also, we identified the optimal clock edge-rate and inter-stage voltage swings in CML gates that achieved minimum transmitter power dissipation. Our analysis results indicate that, when properly optimized, overall transmitter power consumption can be reduced by up to 43% with inter-stage swing optimization with all other design constraints held constant.

A dual-slope capacitance-to-digital converter for pressure-sensing is presented and demonstrated in a complete microsystem. The design uses base capacitance subtraction with a configurable capacitor bank to narrow down input capacitance range and reduce conversion time. An energy-efficient iterative charge subtraction method is proposed, employing a current mirror that leverages the 3.6 V battery supply available in the system. We also propose dual-precision comparators to reduce comparator power while maintaining high accuracy during slope conversion, further improving energy efficiency. The converter occupies 0.105 mm $^{2}$ in 180 nm CMOS and achieves 44.2 dB SNR at 6.4 ms conversion time and 110 nW of power, corresponding to 5.3 pJ/conv-step FoM. The converter is integrated with a pressure transducer, battery, processor, power management unit, and radio to form a complete 1.4 mm $\times$ 2.8 mm $\times$ 1.6 mm pressure sensor system aimed at implantable devices. The multi-layer system is implemented in 180 nm CMOS. The system was tested for resolution in a pressure chamber with an external 3.6 V supply and serial communication bus, and the measured resolution of 0.77 mmHg was recorded. We also demonstrated the wireless readout of the pressure data on the stack system operating completely wirelessly using an integrated battery.

A syringe-implantable electrocardiography (ECG) monitoring system is proposed. The noise optimization and circuit techniques in the analog front-end (AFE) enable 31 nA current consumption while a minimum energy computation approach in the digital back-end reduces digital energy consumption by 40%. The proposed SoC is fabricated in 65 nm CMOS and consumes 64 nW while successfully detecting atrial fibrillation arrhythmia and storing the irregular waveform in memory in experiments using an ECG simulator, a live sheep, and an isolated sheep heart.

We propose a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. A conventional approach to generate these currents is to drop a temperature sensitive voltage across a resistor. Since a large resistance is required to achieve nWs of power consumption with typical voltage levels (100 s of mV to 1 V), we introduce a new sensing element that outputs only 75 mV to save both power and area. The sensor is implemented in 0.18 μm CMOS and occupies 0.09 mm 2 while consuming 71 nW. After 2-point calibration, an inaccuracy of + 1.5°C/-1.4°C is achieved across 0 °C to 100 °C. With a conversion time of 30 ms, 0.3 °C (rms) resolution is achieved. The sensor does not require any external references and consumes 2.2 nJ per conversion. The sensor is integrated into a wireless sensor node to demonstrate its operation at a system level.

Circuit blocks for a 1.5 mm3 microsystem enable continuous monitoring of intraocular pressure. Due to power and form-factor limitations, circuit blocks are designed at nanowatt power levels not completely explored before. The system includes a 75% efficient 90 nW DC-DC converter which is the most efficient reported sub- μW converter in literature. It also includes a novel 4.7 nJ/bit FSK radio that achieves 10 cm of transmission range at 10 -6 BER which is also the lowest number reported for short-range through-tissue wireless links for biomedical implants. A MEMS capacitive sensor and ΣΔ capacitance-to-digital converter measure IOP with 0.5 mmHg accuracy. A microcontroller processes and saves IOP data and stores it in a 2.4 fW/bitcell SRAM. The microsystem harvests a maximum power of 80 nW in sunlight with a light irradiance of 100 mW/cm2 AM 1.5 from an integrated 0.07 mm2 solar cell to recharge a 1 mm2 1 μAh thin-film battery and power the load circuits. The design achieves zero-net-energy operation with 1.5 hours of sunlight or 10 hours of bright indoor lighting daily.

Future biomedical and internet-of-things applications are driving the volume of wireless sensors into the cubic-mm regime. At the mm-scale, complete integration is necessary, and operation within the limits of a micro-battery becomes a primary challenge [1]. With CMOS scaling and ultra-low-power circuits reducing battery volume, the antenna and crystal quickly become the largest components in a cubic-mm node. Higher-frequency operation and silicon-based timing circuits are critical to integrate these components. This paper presents a fully-integrated 9.8GHz impulse-radio ultra-wideband (IR-UWB) radio with an on-chip 2mm monopole and the option of wire-bonding to an off-chip antenna. The crystal is replaced with a novel temperature-compensated relaxation oscillator. Due to modern mm-scale battery limitations, the peak current draw must be

Standby power frequently dominates the power budget of battery-operated ultralow power sensor nodes. Reducing standby power is therefore a key challenge for further power reduction. Applying known circuit techniques for standby power reduction is challenging since standby power of state-of-the-art sensor node systems is now on the order of nanowatts or less. Hence, the overhead of any leakage reduction technique quickly overshadows any gains. This brief proposes an efficient implementation method for super cutoff CMOS that exploits the unique conditions of power gating to enable a highly efficient charge pump design. The proposed techniques are applied to logic blocks and memory devices. For a very low initial standby power value of tens of picowatts, standby power reduction of up to 19.3 × and 29% is achieved for logic blocks and memory, respectively.

Accurate measurement of synchronization cycle time is required for ultra-low power wireless sensor nodes with stringent power budgets. A multi-stage gate-leakage-based timer with boosted charging is proposed to address the high jitter of prior-art gate-leakage-based timers. The key approaches are faster load capacitor charging, wider voltage swing, and an improved gain sensing inverter. The proposed timer reduces RMS jitter by 8.1× and synchronization uncertainty by 4.1×, which allows hourly tracking with 200 ms uncertainty while consuming 660 pW. A novel closed-loop temperature compensation scheme with dynamic leakage adjustment is also proposed to achieve temperature sensitivity of 31 ppm/°C.

The theoretical lower limit of subthreshold swing in mosfets (60 mV/decade) significantly restricts low-voltage operation since it results in a low ON -to- OFF current ratio at low supply voltages. This paper investigates extremely low-power circuits based on new Si/SiGe heterojunction tunneling transistors (HETTs) that have a subthreshold swing of . Device characteristics, as determined through technology computer aided design tools, are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that an HETT-based ring oscillator (RO) shows a 9-19 times reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional mosfets, namely, asymmetric current flow and increased Miller capacitance, analyze their effect on circuit behavior, and propose methods to address them. HETT characteristics have the most dramatic impact on static random access memory (SRAM) operation and we propose a novel seven-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7-37 times reduction in leakage power compared to CMOS.

A 1.0 mm3 general-purpose sensor node platform with heterogeneous multi-layer structure is proposed. The sensor platform benefits from modularity by allowing the addition/removal of IC layers. A new low power I2C interface is introduced for energy efficient inter-layer communication with compatibility to commercial I2C protocols. A self-adapting power management unit is proposed for efficient battery voltage down conversion for wide range of battery voltages and load current. The power management unit also adapts itself by monitoring energy harvesting conditions and harvesting sources and is capable of harvesting from solar, thermal and microbial fuel cells. An optical wakeup receiver is proposed for sensor node programming and synchronization with 228 pW standby power. The system also includes two processors, timer, temperature sensor, and low-power imager. Standby power of the system is 11 nW.

A highly integrated, high-voltage dual-mode boost converter is presented for solid-state drive (SSD) applications, where standby mode efficiency with 100 mA load. To enhance efficiency in light load condition and to achieve wide operation load range, loss minimization by balancing conduction and switching loss is adopted and dynamic power gating scheme is applied for PFM mode operation. Moreover, robust dual mode operation is implemented with time-based control scheme, which enables operation with lower peak current for optimal loss balancing. The proposed converter is fabricated in 130 nm CMOS process with an area of 1.7 mm2. The measured efficiency for supplying 12 V output from 5.5 V input is 91% at its peak and 85% with extremely light load of 200 μA. It also achieves wide load range of 34.6 dB for > 85% efficiency and 18.8 dB for > 90% efficiency.

Recent progress in ultra-low-power circuit design is creating new opportunities for cubic millimeter computing. Robust low-voltage operation has reduced active mode power consumption considerably, but standby mode power consumption has received relatively little attention from low-voltage designers. In this work, we describe a low-voltage processor called the Phoenix Processor that has been designed at the device, circuit, and architecture levels to minimize standby power. A test chip has been implemented in a carefully selected 0.18 mum process in an area of only 915 times 915 mum2. Measurements show that Phoenix consumes 35.4 pW in standby mode and 226 nW in active mode.

With continuous miniaturization of electronic systems, mm-scale sensors are emerging as a future sensor system platform. Recent advancements in mm-scale sensor design is reviewed in this paper. A mm-scale sensor platform and its characteristics are presented and prototype implementation for diverse applications on recent literature are introduced.

We present a 2×4×4mm 3 imaging system complete with optics, wireless communication, battery, power management, solar harvesting, processor and memory. The system features a 160×160 resolution CMOS image sensor with 304nW continuous in-pixel motion detection mode. System components are fabricated in five different IC layers and die-stacked for minimal form factor. Photovoltaic (PV) cells face the opposite direction of the imager for optimal illumination and generate 456nW at 10klux to enable energy autonomous system operation.

Recent advances in low-power circuits have enabled mm-scale wireless systems [1] for wireless sensor networks and implantable devices, among other applications. Energy harvesting is an attractive way to power such systems due to limited energy capacity of batteries at these form factors. However, the same size limitation restricts the amount of harvested power, which can be as low as 10s of nW for mm-scale photovoltaic cells in indoor conditions. Efficient DC-DC up-conversion at such low power levels (for battery charging) is extremely challenging and has not yet been demonstrated.

Electrocardiography (ECG) is a critical source of information for a number of heart disorders. In arrhythmia studies and treatment, long-term observation is critical to determine the nature of the abnormality and its severity. However, even small body-wearable systems can impact a patient's everyday life and signals captured using such systems are prone to noise from sources such as 60Hz power and body movement. In contrast, implanted devices are less susceptible to these noise sources and, while having closer-spaced electrodes, can obtain similar quality ECG signals due to their proximity to the heart [1]. In addition, implanted devices enable continuous monitoring without affecting patient quality of life. As in other implantable systems, low power consumption is a critical factor; in this case to provide a sufficiently long operating time between wireless recharge events.

True random number generators (TRNGs) use physical randomness as entropy sources and are heavily used in cryptography and security [1]. Although hardware TRNGs provide excellent randomness, power consumption and design complexity are often high. Previous work has demonstrated TRNGs based on a resistor-amplifier-ADC chain [2], oscillator jitter [1], metastability [3-5] and other device noise [6-7]. However, analog designs suffer from variation and noise, making them difficult to integrate with digital circuits. Recent metastability-based methods [3-5] provide excellent performance but often require careful calibration to remove bias. SiN MOSFETs [6] exploit larger thermal noise but require post-processing to achieve sufficient randomness. An oxide breakdown-based TRNG [7] shows high entropy but suffers from low performance and high energy/bit. Ring oscillator (RO)-based TRNGs offer the advantage of design simplicity, but previous methods using a slow jittery clock to sample a fast clock provide low randomness [1] and are vulnerable to power supply attacks [8]. In addition, the majority of previous methods cannot pass all NIST randomness tests.

Novel ultra low-leakage ESD power clamp designs for wireless sensor applications are proposed and implemented in 0.18μm CMOS. Using new biasing structures to limit both subthreshold leakage and GIDL, the proposed designs consume as little as 43pW at 25 C and 119nW at 125 C with 4500V HBM level and 400V MM level protection, marking an 18-139× leakage reduction over conventional ESD clamps.

We present a self-adapting power management unit (PMU) for ultra-low power wireless sensor nodes. The PMU uses 1.03nF of on-chip MIM capacitance in a reconfigurable switched-capacitor network (SCN) that automatically adapts to different battery voltages for down-conversion and different harvesting sources/harvesting conditions for up-conversion. The PMU achieves 63.8% / 60.7% down-conversion efficiency at 17.9μW active mode / 12.8nW sleep mode power loading. With the adaptive down-conversion ratio, load power range is improved by 3.76× and 5.48× in sleep and active mode, respectively. We show how the proposed adaptation method enables harvesting with solar, microbial fuel cell, and thermal energy sources, increases harvesting efficiency by 1.92× and achieves the peak extraction efficiency of 99.8% for solar cell.

Bell's Law predicts continual scaling of the size of computing systems, and next of these systems is about to emerge: millimeter-scale sensor nodes. These miniature wireless sensors will enable multiple new applications in a wide range of fields, including medical diagnosis, infrastructure monitoring and military surveillance. However, this form factor remains beyond the capabilities of modern integrated circuit design techniques due to extremely small battery size. This paper describes new circuit design techniques for ultra-low power operations that can be applied to digital processors, memory, power management, and a special focus on standby mode operation, which will bring mm3 sensor nodes into reality.

We propose an ultra-low power optical wake-up receiver with a novel front-end circuit and communication scheme suitable for miniature wireless sensor node applications. Named “FLOW” for Free-space Low-Power Optical Wake-up, the receiver consumes 695pW in standby mode, which is ∼6,000× lower than previously reported RF and ultrasound wake-up radios. In active mode, it consumes 140pJ/bit at 91bps. A pulse width modulated communication encoding scheme is used, and chip-ID masking enables selective batch-programming and synchronization of multiple sensor nodes.

Ultra-low voltage design makes signal level conversion a critical component in modern low power designs. This paper proposes a static level converter operating in the subthreshold regime, called SLC (Split-control Level Converter). Using a novel circuit structure, SLC effectively eliminates the high leakage and short circuit currents in previous approaches. Designed for 300mV to 2.5V conversion and fabricated in 130nm CMOS, measured results show 2.3×, 9.9×, and 5.9× improvements over conventional DCVS structures in delay, static power, and energy per transition, respectively. Even with the smallest area among wide-range level converters, it also has 5.2× smaller standard deviation in delay and only 5.6% change in FO4 delay with 10% V DDL drop, demonstrating robustness.

Designing an ultra-low power sensor node requires careful consideration of the system-level energy budget. Depending on applications, various components can dominate total energy. In this paper, we review three different system energy budget scenarios where any of the microprocessor, memory, and timer of a sensor node can dominate the energy budget. The design space and corresponding trade-offs for these three components are explored to suggest guidelines for the design of ultra-low power sensor nodes.

We propose a low power battery voltage supervisory circuit for micro-scale sensor systems that provides power-on reset, brown-out detection, and recovery detection to prevent malfunction and battery damage. Ultra-low power is achieved using a 57pA, fast stabilizing two-stage voltage reference and an 81pA leakage-based oscillator and clocked comparator. The supervisor was fabricated in 180nm CMOS and integrated with a complete 1 mm3 sensor system. It consumes 635pW at 3.6V supply voltage, which is an 850× reduction over the best prior work.

Recent high performance IC design has been dominated by power density constraints. 3D integration increases device density even further, and these devices will not be usable without viable strategies to reduce power consumption. This paper proposes the use of near-threshold computing (NTC) to address this issue in a stacked 3D system. In NTC, cores are operated near the threshold voltage (∼200mV above Vth) to optimally balance power and performance [1]. In Centip3De, we operate cores at 650mV, as opposed to the wear-out limited supply voltage of 1.5V. This improves measured energy efficiency by 5.1×. The dramatically lower power consumption of NTC makes it an attractive match for 3D design, which has limited power dissipation capabilities, but also has improved innate power and performance compared to 2D design.

Recent work in ultra-low-power sensor platforms has enabled a number of new applications in medical, infrastructure, and environmental monitoring. Due to their limited energy storage volume, these sensors operate with long idle times and ultra-low standby power ranging from 10s of nW down to 100s of pW [1–2]. Since radio transmission is relatively expensive, even at the lowest reported power of 0.2mW [3], wireless communication between sensor nodes must be performed infrequently. Accurate measurement of the time interval between communication events (i.e. the synchronization cycle) is of great importance. Inaccuracy in the synchronization cycle time results in a longer period of uncertainty where sensor nodes are required to enable their radios to establish communication (Fig. 2.7.1), quickly making radios dominate the energy budget. Quartz crystal oscillators and CMOS harmonic oscillators exhibit very small sensitivity to supply voltage and temperature [4] but cannot be used in the target application space since they operate at very high frequencies and exhibit power consumption that is several orders of magnitude larger (>300nW) than the needed idle power. A gate-leakage-based timer was proposed [5] that leveraged small gate leakage currents to achieve power consumption within the required budget (< 1nW). However, this timer incurs high RMS jitter (1400ppm) and temperature sensitivity (0.16%/oC). A 150pW program-and-hold timer was proposed [6] to reduce temperature sensitivity but its drifting clock frequency limits its use for synchronization. The quality of a timer is not captured well by RMS jitter since it ignores the averaging of jitter over multiple timer clock periods in a single synchronization cycle. Instead, we propose the uncertainty in a single synchronization cycle of length T as new metric and use this synchronization uncertainty (SU) to evaluate different timer approaches. The timer period is a random variable X(n), with mean and sigma, μ and σ. Given a synchronization cycle time T, consisting of N timer periods, we define SU as the standard deviation of T as given by √T/μ × σ, assuming X(n) is Gaussian. Note that a smaller clock period increases N and results in more averaging and a lower SU with fixed jitter (σ/μ).

A logic-compatible 2T dual-Vt embedded DRAM (eDRAM) is proposed for ultra-small sensing systems to achieve 8× longer retention time, 5× lower refresh power and 30% reduced area compared with the lowest power eDRAM previously reported. With an area-efficient single inverter sensing scheme designed for R/W speed compatibility with ultra-low power processors, 58% array efficiency is maintained for memories as small as 2kb and for as few as 32 bits per bitline.

Standby power can dominate the power budgets of battery-operated ultra-low power processors, and reducing standby power is the key challenge for further power reduction. State-of-the-art ultra low voltage sensors consume hundreds of nW in wake mode and 100 pW or less in standby mode. Therefore, applying known circuit techniques for further standby power reduction is very challenging. In this paper, we extend known standby power reduction techniques for use in ultra-low power processors. In particular, we propose structures that enable the use of super cut-off voltages throughout the design with minimal power overhead. Different strategies for power gated logic blocks and memory cells are investigated.

The influence of carrier concentration and oxygen vacancy on the performance of amorphous-indium–tin–zinc-oxide (a-ITZO) thin-film transistors (TFTs) is reported. The ITZO TFT with lowest carrier concentration and oxygen vacancy has a high field-effect mobility (μ FE) of 37.2 cm2/V•s, a high on/off current ratio (I ON/I OFF) of ∼1 × 107 and a low subthreshold swing (SS) of 0.93 V/decade. By increasing the carrier concentration and oxygen vacancy, μ FE, I ON/OFF and SS were surprisingly degraded to 14.4 cm2/V•s, ∼4 × 104 and 4.01 V/decade, respectively. By controlling the carrier concentration and oxygen vacancies of ITZO bulk, improvement of the performance in TFT devices can be achieved. The proposed high μ FE of 37.2 cm2/V•s is enough for the application of next-generation displays requiring ultra-high resolution and high-frame-rate displays.