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An oxide fin-based AND flash memory synaptic device is proposed and fabricated using a spacer patterning technology for a hardware-based binary neural network (BNN). A fin-like curved channel structure provides local electric field enhancement, which improves programming efficiency compared to planar-type flash synaptic devices. The fin-based AND flash cell exhibits a high on/off current ratio (>105) with sub-pA off current, and a low programming voltage ( 103) for BNNs. Furthermore, a hardware-based BNN using novel two cell-based synaptic devices arranged in AND array architecture is proposed to implement parallel XNOR operation and bit-counting. Proposed BNN using the synapse model with measured dynamic range and retention property shows only

This paper presents a novel low-power four-stage voltage controlled ring oscillator (VCRO) designed in the TSMC 180 nm CMOS technology. Each stage in the proposed VCRO consists of a differential de...

A single biological neuron can efficiently perform Boolean operations. Artificial neuromorphic systems, on the other hand, typically require several devices to complete a single operation. Here, we show that neuristors that exploit the intrinsic polarity of two-dimensional materials can perform logic operations in a single device. XNOR gates can be made using ambipolar tungsten diselenide (WSe2), NOR gates using p-type black phosphorus, and OR and AND gates using n-type molybdenum disulfide (MoS2) of different thicknesses. To illustrate the potential of the neuristors, we fabricate logic half-adder and parity-checker circuits using a WSe2 neuristor and a MoS2 neuristor in a two-transistor two-resistor configuration, offering an area saving of 78% compared to circuits based on MoS2 gates in a traditional design. We also propose a binary neural network that is based on a three-dimensional XNOR array, which simulations show should offer an energy efficiency of 622.35 tera-operations per second per watt and a power consumption of 7.31 mW. By using two-dimensional materials with different polarities, single neuristors can act as XNOR, NOR, OR and AND logic gates.

To improve the performance of all-digital synthesizable comparators for the stochastic circuit, we present a three-stage rail-to-rail fully synthesizable dynamic voltage comparator. Compared with the state-of-the-art designs, the proposed comparator uses XOR, XNOR, NAND, and NOR logic gates to further improve the comparator’s common-mode input range, offset, speed and power-delay product (PDP). The comparator is implemented on CMOS 45 nm technology, operating with a supply voltage of 250 mV–1.0 V. The comparator has reduced the delay by 0.70 to $$0.82\times $$ , increased the standard deviation of offset by 1.28 to $$1.65\times $$ and reduced the PDP down to $$0.67\times $$ compared to NAND & NOR-based comparator. Hence, these improvements help to increase the performance of the stochastic Flash ADC, and improve the reliability of the stochastic PUF circuit.

The conventional SOA suffers from the problem of the finite gain recovery time that limits its application at higher data rates. Therefore, in the present paper, we employ a carrier reservoir semiconductor optical amplifier (CR-SOA) as an alternative device to realize the all-optical NAND and XNOR logic gates for 120 Gb/s return-to-zero data, for the first time to our knowledge. For this goal, a pair of symmetrical CR-SOAs are incorporated in properly driven and combined Mach–Zehnder interferometers (MZIs), which constitute an appealing technological choice for all-optical switching purposes. The CR-SOA performance is compared against that of the conventional SOA for both considered logic gates. This is done by evaluating the quality factor and associated bit error rate, as well as the quality of the logic outcome. The results reveal the superiority of the CR-SOAs-based MZIs for realizing the logic NAND and XNOR gates at 120 Gb/s by achieving acceptable performance, as opposed to the conventional SOAs-based MZIs for which this is not possible.

Recent studies on neural network quantization have demonstrated a beneficial compromise between accuracy, computation rate, and architecture size. Implementing a 3D Vertical RRAM (VRRAM) array accompanied by device scaling may further improve such networks’ density and energy consumption. Individual device design, optimized interconnects, and careful material selection are key factors determining the overall computation performance. In this work, the impact of replacing conventional devices with microfabricated, graphene-based VRRAM is investigated for circuit and algorithmic levels. By exploiting a sub-nm thin 2D material, the VRRAM array demonstrates an improved read/write margins and read inaccuracy level for the weighted-sum procedure. Moreover, energy consumption is significantly reduced in array programming operations. Finally, an XNOR logic-inspired architecture designed to integrate 1-bit ternary precision synaptic weights into graphene-based VRRAM is introduced. Simulations on VRRAM with metal and graphene word-planes demonstrate 83.5 and 94.1% recognition accuracy, respectively, denoting the importance of material innovation in neuromorphic computing.

Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design?s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation.

Quantum dot cellular automata (QCA) is considered one of the most promising technologies to replace the current CMOS technology. Compared with the traditional transistor technology, the computation relies on a new paradigm based on the interaction between nearby QCA cells. It has significant advantages, such as operating frequency (THz), high device density, and low power consumption. In this brief, a novel XOR/XNOR-function logic gate with two inputs, two enable inputs and one output is proposed and designed in Quantum-dot Cellular Automata (QCA) nanotechnology. In order to demonstrate the functionality and capabilities of the proposed QCA-based XOR/XNOR architecture, performance is evaluated and analyzed. The proposed XOR/XNOR logic gate has a superb performance in terms of area, complexity, power consumption and cost function in comparison to some existing QCA-based XOR architectures. Moreover, some efficient circuits based on the proposed XOR/XNOR gate are designed in QCA.

Tunnel field-effect transistors (TFETs) are being examined as a possible replacement of MOSFETs for digital applications. However, TFETs have small ON-state current and, typically, exhibit reduced speed compared with conventional MOSFETs. Nevertheless, TFETs have some distinct characteristics that can be exploited for digital applications. In this article, using simulations, we show that a single device, in which two terminals are biased independently, can realize all primary two-input Boolean functions, such as AND, OR, NAND, NOR, XOR, and XNOR. By modifying the architecture of double-gate TFET (DGTFET) slightly and appropriately choosing device parameters, the Boolean functions AND, OR, NAND, NOR, and XNOR can be implemented. In addition, we propose a twin double-gate (TDG) TFET architecture, which can implement the inhibition functions $A'B$ and $AB'$ . By suitably combining the inhibition functions, an XOR functionality can be obtained in a single device. These implementations demonstrate that the unique characteristics of TFET, such as ambipolar conduction and dependence of tunneling on the gate–source/drain overlaps, can be exploited to realize logic functions compactly.

In this communication, a new semiconductor optical amplifier (SOA)-based module for multi-valued logic units using the cross-polarization modulation effect is proposed and analyzed. The design is simple and compact, consisting of only three SOAs and a few passive optical elements. SOAs have very low switching power (

Electronic Boolean logic gates, the foundation of current computation and digital information processing, are reaching final limits in processing power. The primary obstacle is energy consumption which becomes impractically large, > 0.1 fJ/bit per gate, for signal speeds just over several GHz. Unfortunately, current solutions offer either high-speed operation or low-energy consumption. We propose a design for Boolean logic that can achieve both simultaneously (high speed and low consumption), here demonstrated for NOT and XNOR gates. Our method works by passively modifying the phase relationships among the different frequencies of an input data signal to redistribute its energy into the desired logical output pattern. We experimentally demonstrate a passive NOT gate with an energy dissipation of ~1 fJ/bit at 640 Gb/s and use it as a building block for an XNOR gate. This approach is applicable to any system that can propagate coherent waves, such as electromagnetic, acoustic, plasmonic, mechanical, or quantum., Typically, Boolean logic gates have to compromise between high speed and low energy consumption which can become limiting at scale. Here, the authors demonstrate architectures for NOT and XNOR gates that enable simultaneous low power and fast operation.

Microring resonator (MRR) is regarded as one of the most widely-used building blocks in photonic integration, which is employed to implement optical filtering, routing, sensing, true time delay, signal processing, logic operations and so on. However, a single MRR intrinsically produces Lorentzian or Lorentzian-derivative shape responses with very sharp peaks, which is incapable of handling wideband signals for microwave photonic systems. In this paper, we introduce a reflective-type MRR with a reflector connected to the drop port of an add-drop MRR. Thanks to the reflector, reconfigurable intensity and group delay responses can be achieved by setting the coupling coefficients of the MRR, leading to the implementation of flat-top filtering, wideband optical true time delay, XNOR/XOR optical logic operation and electro-optic modulation. Both theoretical analysis and experimental demonstration are carried out. This new MRR structure may enable a new, compact and low-cost design strategy for the integrated reconfigurable or programmable microwave photonic systems.

The digital designs operating in sub/near-threshold region are susceptible to timing errors due to the extreme impact of process, voltage, and temperature (PVT) variations. This paper proposes a new error-detecting latch (EDL) to mitigate the impact of PVT variations. The proposed EDL is a single-phase clocked design, which significantly reduces the clock power consumption of the design. The proposed EDL follows a merged and shared architecture of two latches along with an XNOR gate, which leads to a compact layout of EDL. The post-layout simulations in an industrial 28 nm CMOS technology node, show a minimum clock power savings of 31%, average power savings of 16%, and reduction in leakage power by 23% in comparison to the state-of-the-art EDLs at 0.4 V. The 10K rigorous Monte-Carlo simulations across the supply voltage range of 0.23 V - 0.8 V and clock frequency range of 1.6 MHz - 70 MHz shows that the proposed EDL is tolerant to leakage-induced false errors and glitches. SSEDL is robust to process variations even with minimum-sized transistors.

In VLSI system design, one of the most significant areas of on-going research is high speed with low power system design. Usually the speed of the VLSI circuits like binary adders can be improved by more parallelism but, this more parallelism idea will increase the power consumption and area of the circuit. Therefore there is a trade-off between speed and power/area. A carry select adder is one of the fast binary adders but it consumes more power and area. In this paper, we proposed a low power and area efficient and high speed binary carry select adder (CSLA). The half sum and carry generator (HSCG) of the proposed CSLA is designed with a new methodology, that the HSCG output are estimated using input A and B not with carry-in hence it is faster and results in less area leads to low power consumption. Moreover, the NAND gate based circuit is used to compute the intermediate carries within the block and carry-out of the block which are derived from HSCG output along with carry-in. Similarly, the full sum of the proposed adder is generated from XNOR gate based circuitry by utilizing the intermediate carries of the block. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm CMOS technology. The performance of the existing and proposed designs are analyzed and the results shows that the proposed 64-bit CSLA exhibits average reduction of 43% in power and average of 25% less utilization in terms of area compared to existing design. This proposed CSLA is used in a FIR Filter and obtained significant reduction in ADP and PDP.

All-optical signal processing in optical technology is the most reliable process that mitigates the limitations of speed and processing power in electronics by replacing the electronic components with the equivalent optical switching components. All-optical switches are very important in communication and computing, as most communication around the globe is carried on optical fibers. Optical switching is effectively performed in high data rate systems through all-optical gates. The nonlinear signal processing in semiconductor optical amplifier (SOA) is the key element for implementing various optical gate logics. In this paper, combination of optical gates such as all-optical AND, OR, NOT, XOR, NOR and XNOR operations are successfully simulated in single structure. The performance analysis of each gate and its cascaded feature is analyzed by varying the structural and functional parameters of SOA’s active region. The simulation results confirm that the proposed design can be implemented at high data rate of more than 10Gbps with good quality factor and extinction ratio of around 12 dB.

Conventional von Neumann architecture suffers from data trafficking and power hungriness between memory and processing units. Recent architectures escalating to overcome these limitations are near-memory architecture (NMA) and computing-in-memory (CiM) architecture (CMA). Spintronics-based devices, such as spin-transfer torque magnetic memory (STTM), spin-orbit torque magnetic memory (SOTM), differential spin Hall–effect-based magnetic memory (DSHEM), and multilevel voltage-controlled SOT-based magnetic memory (MV-SOTM) are a few promising contenders for post-CMOS technology. MV-SOTM spin device is used in this study to showcase the CMA to perform basic logic operations namely AND/ NAND, OR/ NOR, and XOR/ XNOR within the memory array. Furthermore, magnetic full adder (MFA) is implemented using CMA in MV-SOTM array. The performance of CMA design for MV-SOTM-based MFA is compared with SOTM-based MFA. The proposed CiM design for MV-SOTM-based MFA shows 29.2% and 12.22% performance improvement in terms of write energy and logic power, respectively. Moreover, up to 34% area reduction is achieved in comparison to SOTM-based CiM MFA.

In this study, an InAs channel-based triple gate spin-field effect transistor (FET) model is proposed. The proposed triple-gate spin-FET offers a high density of integration, consumes low power and offers very high switching speed. By incorporating the suitable parameters like channel length, spin diffusion length, channel resistance and junction polarisation, the modelled triple gate spin-FET is then used to implement 3-input XOR, 3-input XNOR and majority gate functions. The designs of 3-input XOR and majority gates were achieved keeping in view that the sum operation of a 1-bit full adder is obtained through XOR gate and the carry operation of 1-bit full adder is obtained through majority gate. Therefore, for designing a 1-bit full adder, only two spin-FETs will be required which signifies the compact nature of the design. In addition, a 2-bit ripple adder is designed with cascading two 1-bit full-adders. Finally, a comparative analysis of the proposed gates and 1-bit full adder with the reported work and conventional CMOS design was carried out in terms of employed number of devices, power consumption and speed. The analysis shows that proposed gates/adder offer better performance than the reported work and conventional CMOS designs.

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, by using which the circuit of AND gate and OR gate composed of memristors is built. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate and the XNOR gate are further realized, and then the adder design is completed. Compared with the traditional gate circuit, this model has distinct advantages in size and non-volatility. At the same time, the establishment of this model will add new research methods and tools for memristor simulation research.

Memristors are a kind of information-storage device with resistance-switching dynamics. Due to the variable conductivity of memristive devices, their composite circuits can be used for implementation of logic operations. In this paper, a novel hybrid CMOS-memristor-based logic circuit is proposed for use in realizing four basic logic operations (AND, OR, XOR, XNOR) simultaneously within the same circuit. Compared with existing logic implementations (MAD Gates, MRL, IMPLY), the present circuit offers better performance and greater efficiency, owing to the significant reduction in the number of memristors used in the circuit and the power consumption. Thus, a new full-adder circuit and a binary-image-encryption circuit are designed. Unlike previous full-adder circuits, the proposed one has great advantages in terms of the number of circuit elements. In the proposed encryption circuit, there are two available encryption methods and the encryption key is independent of the circuit, which can improve the reliability of encryption results.

Recent studies have demonstrated that binary neural networks (BNN) could achieve a satisfying inference accuracy on representative image datasets. BNN conducts XNOR and bit-counting operations instead of high-precision vector-matrix multiplication (VMM), significantly reducing the memory storage. In this work, an analog bit-counting scheme is proposed to decrease the burden of neuron circuits with a synaptic architecture utilizing NAND flash memory. A novel binary neuron circuit with a double-gate positive feedback (PF) device is demonstrated to replace the sense amplifier, adder, and comparator, thereby reducing the burden of the complementary metal-oxide semiconductor (CMOS) circuits and power consumption. By using the double-gate PF device, the threshold voltage of the neuron circuits can be adaptively matched to the threshold value in the algorithms eliminating the accuracy degradation introduced by the process variation. Thanks to the super-steep SS characteristics of the PF device, the proposed neuron circuit with the PF device has an off-state current of 1 pA, representing 105 times improvement compared to the neuron circuit with a conventional metal-oxide-semiconductor field effect transistor (MOSFET) device. A system simulation of a hardware-based BNN shows that the low-variance conductance distribution (8.4 %) of the synaptic device and the adjustable threshold of the neuron circuit implement a highly efficient BNN with a high inference accuracy.

The recent fabrication progress in logic circuits using atomic-scale silicon dangling bond (DB) makes it a promising candidate for field coupled nanocomputing. Moreover, the use of silicon substrate opens the possibilities to integrate DB circuits with existing infrastructure for the complementary metal-oxide-semiconductors (CMOS) devices. However, this emerging technology is still in its initial stage. This paper presents a T-shape structure to realize logic circuits. In addition, fundamental logic gates, such as, two-input AND, NAND, OR, XOR, and XNOR gates, are reported using the T-shape structure. Besides, a novel three-input majority (Si-DBM3) gate and a three-input XOR (Si-DBX3) gate, based on DB pairs, have been presented. Using the proposed Si-DBX3 and Si-DBM3 logic gates, a Full-adder (FA) is designed. All the logic gates are designed and verified using the SiQAD simulation tool.

A novel, energy efficient and power analysis robust logic style called the charge balancing symmetric pre-resolve adiabatic logic (CBSPAL) is proposed to overcome the susceptibility of cryptosystems against side channel power analysis attacks. It employs differential cascode logic tree structure with a pre-resolving feature, which realises improved energy efficiency by minimising non-adiabatic loss and leakage current. The energy efficiency of the proposed logic against static complementary metal oxide semiconductor (CMOS) and other existing secure adiabatic logic styles is proved. Energy deviation for the different input transitions of the individual logic gates, namely, buffer/NOT, AND/NAND and XOR/XNOR is found to be very minimal and it validates the immunity of the proposed logic against power analysis attacks. SPICE simulation of 4-bit add-round structure implementation using CBSPAL shows an energy saving of 89.5% compared to static CMOS implementation at a frequency of 125 MHz. Security of the proposed logic against the side channel power analysis attack is demonstrated by performing the correlation power analysis attacks as applicable for the SPICE simulations. Exhaustive SPICE simulations have been performed using the 32 nm CMOS predictive technology model libraries.

The recent rapid development of acoustic logic devices has opened up the possibilities of sound computing and information processing. However, simultaneous realization of acoustic logic devices with subwavelength size, broad bandwidth and passive structure still poses a great challenge. To overcome it, we propose a subwavelength acoustic logic gate which consists of binary-phase passive unit cells placed into a multi-port waveguide. Based on the phase manipulations of the unit cells, we experimentally and numerically realize three basic logic gates OR, NOT and AND, and a composite logic gate XOR with a uniform threshold of 0.4 Pa based on linear acoustic interferences. More importantly, We also design a composite logic gate XNOR by a four-port waveguide, and composite logic gates NOR and NAND and a logic operation A⊙(B+C) based on two logic gates. We demonstrate a 0.6λ-length, 0.3λ-width, and 0.2-fractional bandwidth acoustic logic gate constructed by passive structures, which may lead to important advances in various applications, such as acoustic computing, acoustic information processing and integrated acoustics.

In today’s technology, optical networking plays a vital role in reducing data losses, thereby providing higher data rates between the transreceivers. The very large scale integration circuits in the modulator–demodulator (MODEM) usually fabricated using complementary metal oxide semiconductor (CMOS) technology have serious scaling limitations; hence, device scaling beyond 65 nm technology becomes highly challenging. Quantum-dot cellular automata (QCA) is one of the most promising nanotechnologies that enable areas of smaller size, i.e. 60% less design area than the CMOS technology, with capability to produce high speed by taking less cycles compared with the other CMOS designs to reduce scaling issues. The QCA-based designs are considered as the best alternative solutions to the transistor-based (CMOS) designs. This paper deals with the implementation of the logic gates NOT, AND, OR, NAND, NOR, XOR and XNOR using both CMOS and QCA technologies, while the QCA allows more possible design structures for each logic gate to enable optimization of the area. Finally, the proposed QCA-based logic gate design and CMOS-based designs are compared in terms of the design area, cell count and the speed of the designs. QCA designer 2.0.3 and virtuoso CADENCE Computer-Aided Design tools are used for carrying out the work.

We present novel techniques for realising reliable low overhead logic functions and more complex systems based on the switching characteristics of memristors. Firstly, we show that memristive circuits have inherent properties for realising multiple valued MIN-MAX operations over the post algebra. We then present an efficient hybrid 1T-4M logic architecture for dual XOR/AND and XNOR/OR functionality, which can be seamlessly integrated with the existing CMOS technology. Although memristors are usually considered to operate at lower frequencies, however, recent advances in technology show their potentiality at high frequencies. To this end, we also explore the effects of high frequencies on their performance and thereby propose reliable high frequency design techniques based on our 1T-4M architectures. Experimental results, based on the design of full adders and multipliers over GF, show that the proposed designs require significantly lower power and overhead while maintaining reliable performance at low as well as at high frequencies compared to the existing techniques.

A series of surface plasmonic logic devices in the terahertz band have been designed, including OR, XOR, NOT, XNOR gates. The basic principle of the logic operation is based on the linear interference caused by the phase difference between the waveguides. The numerical simulations based on the finite-difference time-domain are carried out and the results demonstrate the validity of the proposed method. This approach provides an effective approach for the construction of next generation of integrated circuits.

This paper, proposes a new memristor-based NAND/NOR logic gates using convert Voltage to Memristance (VTM) method. Universal logic gates with similar structure require two different input voltages in order to program the gate to NAND or NOR functions. The proposed structure consists of two input terminals memristors (M in ), and one output memristor (M out ). Gate inputs are voltages and the logic value of M out is the output. Also, other logic gates such as NOT, AND/OR, XOR and XNOR can be implemented using this approach. All of the digital gates and proposed circuits are evaluated using SPICE model of bipolar memristive system with a given threshold. Simulation results show improvement in operation step of the logic gates, higher switching speed, and lower power consumption compared with previous works.

In the recent development of VLSI technologies, the most important difficult case is complexity in power dissipation and heat removal process due to the increasing number of gates per chip. As a result, one of the critical issues in the design of low power VLSI circuits is power dissipation. Adiabatic logic is a promising technique for achieving high performance while limiting the power dissipation in low power VLSI circuits. Self-repairing designs with complete fault coverage are required for industrial applications because it will destroy the arithmetic circuit function. The Self repairing full adder circuit using Efficient Charge Recovery Logic (ECRL) and Positive Feedback Adiabatic Logic (PFAL) has been proposed in this paper. Compared to the existing technique, the proposed full adder circuit consumes almost 30% less power systems and 56% more speed. Compared to the existing system with various design models, the proposed adiabatic logic (PFAL) based low power Self repairing full adder designed by connecting the two XNOR gates act as primary inputs to the sum and carry output of the proposed full adder while a faulty sum and carry is given to the secondary inputs consumes extremely low power and operates at high speed. The proposed Self repairing circuit detects the fault with low power consumption in complex circuits. Proposed structure consumes lower area overhead relative to the traditional self-repairing circuit.

Quantum-dot cellular automata (QCA) is a new and considerable technology for implementing nanoscale electronic circuits. QCA technology is considerable in terms of high speed, area and low power consumption compared to CMOS technology and can significantly improve the design of various logic circuits. The XOR/XNOR gate is one of the basic components in a full adder circuit, and improving its performance can lead to an improved full adder. To this end, the purpose of this paper is to provide a new and efficient design for the XNOR circuit based on QCA technology in order to realize the implementation of the new full adder structure. In order to evaluate the efficiency of designed structures, their operation has been studied by QCADesigner software. The simulation results show the superiority of the proposed full adder structure in terms of cell reduction about 5 %, 33 % in latency (clock zones) and 25 % in area reduction compared to the previous structure.

Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM (RRAM)-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered. The proposed design uses 65 nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2, consumes 13.6 pJ of energy per 1 k query within 10 ns clock cycle. It shows a reduction of ~ 31 × in area and ~ 3 × in energy consumption compared to fully digital ASIC implementation using 65 nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area.

This paper highlights the implementation of all-optical mode alteration using a simple micro-ring resonator (MRR). The polarization-based switching happens if a suitable input polarized light is applied as a source and pump power. The mode-conversion with respect to change in the behavior of the input and in the pump signal is used to realize all-optical OR/NOR and XOR/XNOR logic gates in both the output ports of the single MRR simultaneously. The all-optical switching behavior is also justified by its time-graph. The model is verified using the finite-difference time-domain simulation approach. Some characteristics parameters are also explained to highlight its benefits. The architecture may also be used to design new polarization-conversion centered logical and arithmetic circuits.

To design a full adder device using Hybrid Logic style and XOR-XNOR cell based module plays a vital role in the modern semiconductor industry. The critical microelectronic circuit parameters such as power, delay, Power Delay Product (PDP) and driving capability based on the hybrid logic full adder circuit is mostly dependent on the performance of XOR-XNOR logic cell. This article explores the comparative study of D.Radhakrishnan, Chang et al, Valashani-Mizrakuchaki, Naseri-Timarchi and Jyoti-Abhishek projected XOR-XNOR cells, which are used in hybrid logic style, based full adder circuits. The different input combination versus outputs for various charging and discharging paths of the different XOR-XNOR cells are tabulated. The projected logic digital circuits are executed with supply voltage 1.8 V. The digital design parameter such as power, delay, output referred noise and PDP are calculated to validate the various XOR-XNOR circuits used in hybrid logic based full adder.

In this paper, two novel hybrid adder designs, namely, FHAS-1 and FHAS-2 have been proposed. These designs are designed using multiplexor, XOR and XNOR gates and they can be operated as both adder and subtractor modules effectively. A hybrid logic design principle has been utilized to construct the circuit structures. Transmission gate structures have been employed to realize the multiplexor design which determines whether addition or subtraction operation has to be performed by circuit. These circuits are designed using BSIMCMG FinFET 32nm technology files and the simulation is carried out using Cadence® Virtuoso tool. It is demonstrated that the proposed circuits incur lower power consumption and reduced delay compared to existing adder and subtractor circuit counterparts. Proposed circuits have been analyzed in terms of varying load and changing supply voltage conditions and the efficiency of FHAS-1 and FHAS-2 have been validated. It is observed that proposed FHAS-1 circuit is 81.25%, 42.13%, 25% and 13% more power efficient than the hybrid full adder circuit counterparts such as HFA -19T, HFA -22T, HFA -26T and HFA -17T, respectively.

This work analyses a set of approximate full adder circuits in 7nm FinFET device technology in order to identify how energy-efficient these designs are for different voltage operation points. The behavior in a specific environment with voltage scaling is compared to conventional exact adders. The results allow designers access to the pros and cons of each design in error-tolerant applications. Considering the impact on delay and power consumption, approximate XNOR and PTL based FAs showed increase in PDP for all voltages applied. However, Mirror Adder inspired approximate designs showed a reduction in PDP at 0.4V. The PDP for buffer approximated FAs remained constant throughout voltage scaling.

In this paper, optimized designs of two 4-bit adders, namely ripple carry adder and look-ahead carry adder have been presented. These adder circuits are highly efficient in terms of delay, power, and PDP. A 1-bit hybrid full adder, which is the basic unit of the presented designs, is constructed using XOR and XNOR gates. Thus, energy-efficient XOR-XNOR gates are employed in the construction of 1-bit full adder and this adder when compared with conventional CMOS-based full adder, is found to have superior performance. This hybrid full adder cell is further used to implement the two 4-bit adders using Cadence Virtuoso EDA tool. The simulations, carried out at 45-nm CMOS process technology in a range of 0.6–1.2 V supply voltage, indicate that presented designs are superior in speed and power as compared to their conventional CMOS-based counterparts.

Different adder structures have been reviewed with CMOS logic and hybrid logic styles in this paper. XOR/XNOR cell, which is the key element in full adder design was also reviewed. Hybrid adders have advantage of low delay and low area occupancy due to less transistor count used. Lower value of PDP also can be achieved with hybrid structures. Adder structures are implemented in this paper by designing XOR and XNOR cells. Critical path estimations are made and number of transistors in critical path helps in estimating the critical path delay. Delay comparison for several adders was reviewed.

A 65nm XNOR-SRAM macro is presented for binary deep neural network (DNN) accelerator. It features 1) a custom XNOR-SRAM bit-cell design with 8 transistors (8T); 2) a fully parallel compute-in-memory capability of XNOR bit-counting for the inference. Multi-level sense amplifier is employed as Flash analog-to-digital converter (ADC) at edge of the array. The impact of ADC offset on the algorithm-level accuracy is statistically evaluated on a VGG-like XNOR-Net with the CIFAR-10 dataset, showing a marginal degradation ~1.77%. Read-disturb of SRAM bit-cell during parallel computation is also evaluated and its impact is minimized by lowering the word-line (WL) voltage. Silicon measurement results show that the proposed XNOR-SRAM unit-macro achieves a fast access time (2.3 ns) for parallel bit-counting and a high energy efficiency (44.8-62.8) TOPS/W depending on the WL voltage.

This paper presents the first experimental demonstrationof a ternary memristor-CMOS logic family. We systematicallydesign, simulate and experimentally verify the primitivelogic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.

In this communication, we are going to design a new all-optical SOA based XNOR gate using tree architecture implementing the cross-polarization modulation (XPolM) effect in semiconductor optical amplifier (SOA). We get some good values related to quality factor (Q~62 dB) and some other performance-related parameters associated with a very high speed (~100Gbit/s) of operation.

We have monolithically integrated RRAM array with oxide semiconductor channel access transistor in 3D stack, achieved uniform memory characteristics of 1 T1R cells at each layer, and demonstrated basic functionality of XNOR operation as in-memory computing for binary neural network AI applications, for the first time. The impact of RRAM bit error rate on neural network is also investigated. 3D neural network built by this architecture has high potential to enable area-efficient, low-power and low-latency computing.

In this paper, multiplexer based logic gates design is presented using ballistic deflection transistor. The three-parameter gaussian peak analytical model is integrated into behavioral modeling in the Verilog-AMS module to achieve the characteristics of ballistic deflection transistor. Also, the device is modeled and simulated on the Cadence AMS simulator and further the single ballistic deflection transistor is used to design the inverter/buffer circuit. The two ballistic deflection transistor is used to design the logic gates, which are based on the 2:1 multiplexer structure. The simulated results confirm the correct working of all logic gates.

Miniaturization of semiconductor industries paved the way for rapid development in the field of digital electronics. In DSM range, power dissipation has become a major concern due to leakage currents; hence, researchers are continuously trying to evolve ways to mitigate this. Out of many such ways the use of carbon nanotube technology is a promising way to design low-power circuits, as carbon has a property of providing variable threshold voltage (VTH) in N-type transistors. Here simulation results confirm that CNTFET has better performance than MOS and FinFET technologies in low-power world. In this paper existing and proposed adiabatic logic is implemented by CNTFET technology at 32 nm in HSPICE by using Predictive Technology Model (PTM). Comparison of simulation results shows that proposed CNTFET-based ON–OFF-DCDB-PFAL adiabatic logic saves average power 94.33% in Buffer/NOT, 93.13% in NAND/AND, 93.14% in NOR/OR, 91.76% in XOR/XNOR when compared with 2N2N2P circuit at 10 MHz frequency.

QCA technology is an emerging and promising technology for implementation of digital circuits in nano-scale. The comparator circuits play an important role in digital circuits. In this work, a new and efficient coplanar 1-bit comparator circuit is proposed and evaluated in the QCA technology. The designed coplanar 1-bit QCA comparator circuit is constructed based on majority gate, XNOR gate and inverter gate that are designed carefully. The functionality of the designed coplanar 1-bit QCA comparator circuit is verified by using QCADesigner version 2.0.3. The obtained results indicate that the designed 1-bit QCA comparator circuit requires 0.03 ?m2 area and 38 QCA cells. It also has 0.5 clock cycles delay. The comparison demonstrates that the designed QCA comparator circuit provides improvements in comparison with other QCA comparator circuits in terms of effective area, cell count, and delay as well as cost.

Using the knowledge that any gate can be built through different arrangements of micro-ring resonators, this paper proposes the all-optical design of XOR and XNOR logic gates. The gates structure thus consists of micro-ring resonators (MRR) paired with a constant source of light (COS). MRRs in these designs are utilized as modulators by tuning their resonant wavelengths. In this way, under no external disturbances, the rings are uncoupled by default. The proposed devices are CMOS-compatible meaning that they can be fabricated using the existing technologies. Also, to reduce the fabrication complexity of the proposed devices, thermo-optic modulation is employed as primary light modulating technique. The logic gates are tested at 25 kpbs. Device parameters are provided as well for manufacturing purposes. The study concludes with suggestions on design improvements and potential application of the optical gates.

In this paper, a new topology for dynamic logic-based full adder is proposed and analyzed. The XOR and XNOR gates are generally used as basic logic blocks in the full adder design. In this work, the modified architectures of XOR and XNOR logic gates are used in the implementation of full adder circuit. The suggested topology of XOR/XNOR gates exhibits a full logic swing. The proposed full adder circuit is simulated using the conventional 180 nm CMOS process technology. The simulation results using SPICE simulation tool demonstrate that there are substantial improvements in power dissipation and speed of the proposed circuit compared to the earlier reported designs.

In the quest for novel, scalable and energy-efficient computing technologies, spin-based logic devices are being extensively explored due to their potential for nonvolatility, small cell area, and low operational power. Spin torque majority gate (STMG) is one of the most promising options for beyond CMOS nonvolatile logic circuits for normally-off computing. However, significant problems arose with cascade-ability, signal nonreciprocity, and complicated circuit configurations based on STMG. In this paper, a novel magnetic majority gate (MMG) logic has been proposed, utilizing both spin transfer torque and spin–orbit torque effects. A logic family including and/nand and or/nor functions can be achieved with an easy configuration and under a stable operation. Communication between logic units is realized by spin current injection through a nonferromagnetic metal wire to ensure its cascade-ability and nonreciprocity to design multiple logic-depth circuits. With all of these advantages, the proposed cascadable MMGs can be utilized to design logic functions such as the BUFFER/ NOT, XOR/ XNOR, and complicated logic gates, which pave the pathway for designing robust and comprehensive logic circuits using full spintronic devices.

In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-swing XOR–XNOR or XOR/XNOR gates. Each of the proposed circuits has its own merits in terms of speed, power consumption, power-delay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive HSPICE and Cadence Virtuoso simulations are performed. The simulation results, based on the 65-nm CMOS process technology model, indicate that the proposed designs have superior speed and power against other FA designs. A new transistor sizing method is presented to optimize the PDP of the circuits. In the proposed method, the numerical computation particle swarm optimization algorithm is used to achieve the desired value for optimum PDP with fewer iterations. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the size of transistors.

In recent years, there is a trend towards the development of reconfigurable circuits where devices using them offer flexibility and performance. Different technologies are explored, such as threshold logic gates (TLGs), which are one of the most promising future technologies, and researchers are examining and improving different characteristics such as density, performance and power dissipation. This research presents a 4-bit arithmetic logic unit (ALU), which was designed using TLGs through reconfigurable logic blocks with a universal circuit configured with three stages based on a floating-gate metal oxide semiconductor transistor with more than one control gate, which was named neu-complementary metal oxide semiconductor (ν-CMOS). The main contribution is that this device is configured as a ν-CMOS inverter and has the ability to program the threshold voltage of its transfer curve by applying an external voltage to the additional control gates. The number of input bits and the magnitude of the weighted input capacitances related to control gates of the ν-CMOS inverters is obtained and analyzed by using the graphical method (floating-gate potential diagram). Finally, the proposed 4-bit ALU shows similar results as those measured from the ALUs implemented in the field programmable gate array evaluation kit and the Motorola chip MC14581B.