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Though Current Mode Logic has excellent features like higher switching speed and reduced crosstalk due to small output swing, there exists numerous flaws such as static power dissipation, non-suitable for power-down modes and comparably higher design complexity of load resistors. To address the aforementioned worries, this article incorporates a dynamic current mode design approach having active load and controlled current source to configure an improved (2/3) dual modulus prescaler. Simulation results of the proposed circuit using Cadence Virtuoso platform for 90 nm CMOS at 1.2 V supply depict a power consumption of 2.517 mW when driven by a high frequency of 2 GHz. The phase noise and output noise are found to be − 147.001 dBc/Hz and − 181.7 dB at 1 MHz offset while it reads a self-oscillation frequency of 5 GHz. The variation tolerance of the design is proved via 5% skew-based simulation at all corners; whereas the correct functionality at 28 nm UMC justifies its scalability.

CMOS integrated circuits consisting of MOSFETs have tradeoffs among their performance parameters. Hence they need minimization in those tradeoffs calling for multi objective optimization to yield a circuit with enhanced characteristics. To perform simultaneous optimization of the Phase locked loop (PLL) performances using an effective multi objective optimization technique saving the designer’s time and causing the near best performance is the motivation of this work. Though the designer can optimize the circuit in the netlist level, it is less effective and a time consuming iterative process and sometimes it is next to impossible for complex and nanoscale circuits with large number of MOSFET devices and interconnects. Performance parameters like phase noise, lock time and power consumption are optimized subject to the practical design constraints using an efficient multi-objective optimization technique, infeasibility driven evolutionary algorithm (IDEA) in a real time environment. Using design parameters like the channel length and width of the MOSFETs for optimal performance, the PLL is simulated for model validation. Significantly superior performance achieved by the designed PLL is demonstrated. The phase noise, average power consumption and lock time achieved here are −126.3 dBc/Hz at 1 MHz offset frequency, 1.523 mW and 50 nS respectively.

The latest electronic gadgets demand many functionalities which requires enhanced performance of the processor. To ensure this, cache based on Static Random Access Memory (SRAM) is a vital part in electronic devices. Above 90 nm technology, we can build an SRAM in CMOS LSI technology without electrical stability, by connecting six transistors. However, leakage and variability of transistors in SRAM cell have become dominating factor below 90nm technology. So we must design SRAM bit cell with utmost care. Recently SRAM cells have been designed to deal with these problems. However, it is an important task to achieve a balanced performance between all SRAM cell parameters of sub-nanometer technology. A new design of SRAM is presented in this paper to elevate the performance. The proposed SRAM is designed and implemented in CMOS 90nm technology and produces comparatively better performance in terms of Static Noise Margin (SNM), stability and power dissipation when compared with conventional 6T SRAM. The cell reduces the energy consumption by using the technique of stacking. The stability of proposed SRAM is also high compared to recent designs.

This work has been paying attention to design and implement a Transmission gate phase frequency detector (TG-PFD) for Fast locking and low Reference Spur PLL working in Giga-Hertz choice. It has been experiential that the projected TG-PFD could completely erase delay for reset thereby eliminating dead region and blind region as well. By inclusion of the transmission gate into the PFD, could enhance the magnitude of the output signal and hence could improve the loop band and obtained a PLL with reduced locking time. Leakage current minimized as a result of adding CMOS inverters at the output of the TG-PFD and thereby obtained better reference spur for the Phase Locked Loop implemented using TG-PFD. Reference Spur of −77.2 dBc, locking time of 2.83 µs have been obtained for the designed PLL using projected TG-PFD in 180 nm CMOS technology which is exactly matching with the mathematical analysis done by this paper.

The read instability of conventional 6T-SRAM cell has made the 8T-SRAM cell a substitute for high data reliability. But the single ended nature of read operation demands a complete Vdd swing of high capacitive read bit lines leading to large energy consumption. A novel assist technique using charge recycling concept is proposed here which reduces the read and write energy by reducing the voltage swing. Mathematical analysis of the proposed technique, theoretically predicts the read and write energy to reduce by 75% and 25% respectively compare to that of the conventional 8T-SRAM array. Experimental simulation using predictive technology model demonstrates these two energy consumptions to be reduced by 58% and 27% respectively. The proposed technique also reduces the leakage current flow in the standby cells and hence the energy consumption. The dummy read current flow in the half-selected cells is also controlled significantly in the proposed technique. The stability of the SRAM cell remains unchanged by the insertion of the proposed assist technique.

The impact of alpha particle and exposure to cosmic radiation has multifold the existing stability issue associated with modern sub-100 nm SRAM cell design. Noise insertion in the half selected cell of a SRAM array is another serious issue which degrades the stability of a cell as well as waste energy through the half selected cells. The proposed highly stable 8T-SRAM cell takes care of both the above mentioned issues effectively. The cell is capable to be arranged in a bit-interleaving fashion which can then use a conventional error correction code (ECC) to correct the single bit error caused by the exposer to cosmic radiation. Traditionally the read stability and write ability are conflicting to each other and any one of them can be enhanced with sacrificing the other. But the proposed cell enhances both the read stability and the write ability simultaneously. Two other cells namely the 8T differential (8T-DIFF) SRAM and 9T read disturbance free (9T-RDF) SRAM are compared with the proposed SRAM cell which consume 20.1% and 16.2% more energy respectively. The read speed of the proposed SRAM is significantly higher than the 9T-RDF SRAM and marginally higher than the 8T-DIFF SRAM. The write speed of the proposed SRAM is also better than the two compared SRAM.

Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.72.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX.

In modern SOC design SRAM has become an integral part owing to its capability to form a bridge and overcome the speed mismatch problem between the high speed processor and the low speed data storage devices. Because of the read and write operation of SRAM cell having conflicting transistor sizing requirement, it is very difficult to maintain the transistor size to satisfy both the needs. The destructive nature of read operation enforces a serious thought about SRAM cell data stability. Transistor sizing and cell stability already being a critical problem becomes even more critical when we consider the process and temperature variation. Thus the SRAM should be designed with keeping the process and temperature variation in mind. The random fluctuation in device parameters such as transistor width, length, oxide thickness, oxide capacitance and doping concentration leads to variation in the threshold voltage and other transistor characteristics. The change in these transistor characteristics alters the SRAM cell performance. Hence this should also be taken care of to ensure the cell performance to be in the desired range even in presence of random fluctuation during fabrication process. The various performance measure such as SNM, write SNM, speed and power consumption must be tested under worst process corner as well over a wide temperature range to ensure that they lie in the acceptable range during worst operating condition. Also these parameters must be tested using Monte Carlo simulation to ensure a robust operation in presence of random fluctuation during fabrication process.

This paper presents the performance of SRG Tunnel FET biosensor. Here the different device parameters are deliberate to meet the requirement of the technological development. Focus is made on how TFET can be a substitute ahead of CMOS characteristics for biosensor mean and to more enhance the low power design policy to facilitate it for IOT purpose. There is a experimentally demonstration has been done for nanogap cavity A nanogap cavity region. Investigation of the staggered gap hetero junction SRG TFET was done. The results are obtained using Silvaco software.

Blind zone of a phase frequency detector (PFD) enhances the phase noise in a Charge Pump PLL. This paper presents a novel technique to reduce the blind zone which reduces the reference spur as well. In this proposed work a variable delay element is incorporated in the Reset path of the PFD. The overall PFD delay is maintained at a small positive value to avoid blind zone at lower phase noise. The performance analysis carried out in Cadence design environment and compared with the performance of a PFD using a fixed delay element in its reset path. The comparison shows that the phase noise is improved by 6 dB.

Read noise insertion problem of conventional read method of 6T-SRAM cell has forced to think about indirect read. Indirect read though eliminates read noise insertion but also take away the capability to use differential sensing thus leading to more energy and time consumption. Charge recycling concept must be followed by the SRAM cell to reduce energy consumption. An indirect read technique based SRAM is proposed which is capable to follow differential sensing along with following charge recycling technique. Thus it makes the proposed SRAM cell high stable, fast and low energy consuming. Theoretical estimation states that write and read energy consumption of the proposed cell is 12.5% and 25% smaller than those of the compared RDFD-SRAM. Stability analysis shows that the read SNM of the proposed cell which is the most critical stability index is same as its retention SNM and is 317% of the read SNM of conventional 6T-SRAM. The delay analysis also states the fastness of proposed cell.

In this paper, current starved voltage controlled oscillators (CSVCO) using CMOS 180 nm technology are designed and their performances are evaluated. Then, a comparative study of different topologies of CSVCO like five-stage and seven-stage CSVCO is performed on the basis of power consumption, phase noise, center frequency, and tuning range. The simulation results reveal the better performance of the proposed design as compared to existing current starved VCO in terms of phase noise and power consumption.

In a system though the analog circuits occupy very less space but they require far more design time than the digital circuits. This is due to the fact that the number of performance measures of an analog circuit is more than those for digital circuits. Predicting and improving the performance, robustness and overall cost of such systems is a major concern in the process of automation. In the automation process, optimization of performances subjected to a verity of environmental constraints is a central task. In this chapter, efficient analog circuit sizing techniques and their optimization are surveyed.

In the era of nanotechnology, leakage current, active power, delay, area bear an important metric for design and analysis of complex arithmetic logic circuits. In this paper major work has been done in determining leakage current, power and their analysis. Different full adders such as 28T, 14T, 11T and 10T have been designed and implemented in ALU. The 10T full adder has been designed by using optimal sleep transistors in reverse bias which can minimize leakage power as compared to other full adders. A comparison has been made among all these adders and the most efficient adder is obtained. We have performed full adder simulations in cadence virtuoso 180nm technology and simulations have been compared for low leakage power. The thesis not only concentrates on the design but also implementation has been done in obtaining the arithmetic logic unit block.

Dead zone very often poses to be a limitation in the high performance Phase Locked Loops (PLLs). The design of a dead zone free PLL with low phase noise and fast locking capability is proposed. This is achieved by using a voltage variable delay element (VVDE) in the reset path of the Phase Frequency Detector (PFD). A feedback from one of the inputs of charge pump circuit is used to maintain the overall PFD delay at a small positive value to avoid dead zone at lower phase noise. The PLL performance with this proposed PFD is analyzed in the Cadence design environment.

Charge Pump in a phase locked loop (PLL) generates non-ideal effects such as current mismatches at the output node and switching errors at the pull up and pull down networks. This work presents a novel transmission gate cascode current mirror charge pump circuit. The switches incorporated in this work are Transmission Gates which help to reduce various switching errors, and only one supply independent reference current source is used to have a minimum current mismatch. The performance analysis carried out in the Cadence design environment, and it is observed that the loop locks in 25 ns which is 50 % faster than the conventional charge pump. The control voltage absolutely has no ripple in it after locking which reduces the reference spur further. It could be achieved because the current mismatch is only about 7 %. This PLL operates at 2.5 GHz having a wide lock range of 0.5---2.8 GHz where average power consumption is 1.74 mW. Due to the use of cascade current mirror circuits, the output voltage swing that can be obtained is 1.79 V.

Low power consumption, low phase noise and dead zone free operation are the vital performance parameters in a high performance Phase Locked Loop (PLL). These parameters are tailored by using a variable controlled delay element in the reset path of the Phase Frequency Detector (PFD) of a Charge Pump PLL (CPLL). The overall PFD delay is maintained at a small positive value to avoid dead zone at lower phase noise by using feedback from one of the inputs of the charge pump. The performance analysis carried out in Cadence design environment is reported in this work.

This paper explores a Phase Locked Loop (PLL) design that can satisfy a wide range of frequency which can be used for GSM application. PLL is used for the wireless communication in the GHz range to correct the phase and frequency error and provides synchronization with low locking time, reduced skew and jitter. The PLL is used inside many processing elements to provide clock synchronization and clock recovery. Above important applications call for the design of a Phase Locked Loop with low phase noise, low lock in time and high capture range. The design of this PLL is performed in 90nm process technology (GPDK 090) in cadence virtuoso Analog design environment which achieves a frequency range of 250 MHz to 950 MHz. This PLL has phase noise of -91.74 dBc/ Hz at 1 MHz of offset frequency where the lock in time is 220 ns which is considerably less.