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New transmission techniques for short-reach optical transmission applications especially datacenter interconnections are highly expected to break current bandwidth bottleneck, among which mode division multiplexing (MDM) based on few-mode fiber (FMF) is promising by exploring different linearly-polarized (LP) modes or mode groups as spatial transmission channels. However, it has been a great challenge to deal with degenerate modes in FMFs. In this paper, a FMF design utilizing multiple ring perturbations in fiber core to suppress modal crosstalk during fiber transmission is firstly proposed and a 6-LP-mode double-ring-core (DRC) FMF is fabricated with a high minimum refractive index difference (min|neff|) of 1.4910-3 among all the modes. Secondly, a novel degenerate-mode-selective coupler (DMSC) converting each degenerate LPmn mode into the LP11 mode in a two-mode fiber is proposed. Then intensity-modulation/direct-detection (IM/DD) MDM transmission scheme without any digital signal processing (DSP) can be realized utilizing mode multiplexer/demultiplexer (MUX/DEMUX) consisting of cascaded mode-selective couplers (MSC) and DMSCs, in which each degenerate or non-degenerate LP mode is considered as an independent transmission channel. Then based on the proposed DRC-FMF and mode MUX/DEMUX, we demonstrate a 4-LP-mode prototype system using commercial single-mode 10 Gbps SFP + modules and 4K video transceivers without any hardware or software modifications. Finally, the intra-LP-mode dispersion (ILMD) effect in a weakly-coupled FMF is analyzed and a modified fixed-analyzer method is proposed for its measurement. Experimental results show that it may be one of the major impairments for IM/DD MDM transmission.

To cancel the multipath self-interference at the receiver of a wideband in-band full-duplex (IBFD) multiple-input multiple-output (MIMO) radio-over-fiber (RoF) transmission system, a photonic-assisted approach is proposed and experimentally demonstrated. A multipath optical tunable delay line (MOTDL) module with a large adjusting arrangement and high tuning precision is designed to manipulate the local reference signals, which are modulated onto several optical wavelengths and then poured into the MOTDL via a dense wavelength division multiplexer (DWDM). By tuning the time delay and attenuation of each path in the MOTDL, all the self-interference signals can be cancelled from other local transmit antennas of the MIMO RoF transmission system, and the desired radio frequency (RF) signal can be recovered. A proof-of-concept experiment is carried out to verify the feasibility. Results show that at the receiver of a 3 3 MIMO RoF transmission system, the multipath self-interference cancellation depths of 30.18 dB, 24.9 dB, 22.7 dB, and 20.88 dB at 16.6 GHz are achieved for the bandwidths of 100 MHz, 500 MHz, 1 GHz, and 2 GHz, respectively.

This article presents a 220-GHz four-channel, noncontiguous, and manifold-coupled waveguide multiplexer for future terahertz (THz) multichannel communication application. The multiplexer is composed of four Chebyshev bandpass filters based on metal waveguide technology. Through a unique design in which the tuning dimensional variables are reduced to 14 and a co-design of low-order electromagnetic (EM) distributed models and full-wave EM models, the design optimization is achieved with a good computational efficiency and design accuracy. The proposed multiplexer is fabricated by high-precision computer numerical control (CNC) milling technology, in which the fabrication errors are evaluated to be within ±3 μm. The measured results exhibit 1.7 dB of in-band insertion loss and better than 15 dB of average common-port return loss for each of the channel filter. The measured results are all in good agreement with the simulated ones, thereby validating the complete design procedure.

A novel approach to de‐embed the frequency response of filters connected to a 2‐channel multiplexer without the need for unplugging is proposed. The technique to manifold coupled multiplexers with arbitrary number of filters is also theoretically generalised. In multiplexer tuning, there are practically important circumstances in which it is advantageous to de‐embed the frequency response of filters in multiplexers without detaching them. The authors show that using a novel technique and reasonable approximations, all filters of a multiplexer can be modelled by simple microwave networks, and then, the equivalent rational function of the channel filters can be estimated appropriately by the rational H2 approximation; extraction of this model facilitates tuning of the filters using the coupling matrix method. The impact of mechanical tolerances on the accuracy of the proposed technique is also studied. Next, this method is examined on a 2‐channel multiplexer and its application in de‐embedding and tuning of its connected filters is verified. Provided that the mechanical tolerances of the structure are sufficiently small, this technique is a powerful engineering solution towards tuning of manifold‐coupled multiplexers.

This paper aims to propose two new all-optical configurations to realize the behavior of four inputs-single output (4:1) multiplexer logic. The presented schemes are designed by using micro-ring resonator (MRR)-based all-optical switches. The first proposed configuration is based on a new logic design of multiplexer and employs only eleven MRRs. To get further better system compactness and speed, one more all-optical implementation of 4ː1 multiplexer has been developed employing only seven MRR structures. By using seven MRR-based all-optical realization of 4ː1 multiplexer, an all-optical multifunction reconfigurable logic gate structure has been developed which can be reconfigured optically to perform different logic operations. The switching activity of MRR can be considered as the backbone of the proposed circuits and has been discussed in detail with mathematical explanations and MATLAB simulations. The logical behavior of the presented seven MRR based all-optical multiplexer and the all-optical multifunction reconfigurable logic gate has also been validated by performing MATLAB simulations.

Quantum-dot cellular automata (QCA) is a rapidly intensifying nanotechnology that promises ultra-low power consumption, high speed, and ultra-small area requirements. Multiplexer and demultiplexer are the two fundamental and unavoidable blocks in quantum computation or nano communication using QCA. Two significant factors in evaluating the performance of a QCA circuit are energy dissipation and cost function. The total energy dissipation of the QCA multiplexer is 13 meV, whereas, the total energy dissipation of the demultiplexer is 10.4 meV utilizing QDE. The total energy dissipation of the multiplexer employing QCAPro at a fixed temperature of 2 K and a tunneling level of γ = 0.5EK is 21.67 meV, while the same for demultiplexer is 32.86 meV. The Runge–Kutta approximation approach was used to estimate energy using the tool QDE in the Coherence vector energy mode. In addition, the costs of both experimental objects have been determined. Multiplexer and demultiplexer area-delay costs (m2-cc) are 0.002 and 0.005, respectively; multiplexer QCA-specific cost is 90 scp, and demultiplexer QCA-specific cost is 20 scp; multiplexer and demultiplexer energy-delay costs (seV–scc) are 0.000206 and 0.000429, respectively.

The increasing demand for high-speed information transmission as a result of adoption of wide variety of multimedia applications including high-definition television, social networking, and live streaming etc. has challenged the service providers. The conventional wireless transmission systems based on radio frequency are unable to meet the high channel capacity requirements. We design and demonstrate a novel radio-over-free space optics (RoFSO) communication system using hybrid wavelength- and mode-division multiplexing (WDM-MDM). The present RoFSO system consists of four transmitter subsections, four-channel MDM multiplexer/demultiplexer, four-channel WDM multiplexer/demultiplexer, and four receiver subsections. Each channel uses four distinct spatial modes (HG00, HG01, HG02, and HG11) which transport independent 10-Gb/s-10-GHz information over a wavelength range of 850–852.4 nm. We achieved a net system transmission rate of [4 $$\lambda \times$$ (4 modes) $$\times$$ (10 Gb/s-10 GHz)] i.e. 160-Gb/s-160-GHz. Also, we demonstrate the WDM-MDM-based RoFSO link performance and availability under clear and dust weather conditions using bit error rate, maximum reachable link range and eye diagrams as key performance evaluation parameters. The results showed a successful data transfer through 8 km clear weather free-space channel and 88 m dense dust weather conditions, respectively. Subsequently, the results show the feasibility of presented system in the implementation of high-speed ultra-dense cellular/data 5G networks (above 6 GHz) and smart city applications.

This article presents a 120-GS/s 2:1 8-bit analog multiplexer (AMUX) in SiGe-Bipolar CMOS (BiCMOS) technology that exhibits the highest effective resolution reported for an AMUX in any kind of semiconductor technology. This article presents the design considerations that have led to this high resolution. In particular, it contains a discussion on the choice of an AMUX circuit concept to support high linearity. A frequency-domain explanatory model for the signal contribution to the effective number of bits (ENoB) in the presence of mismatch errors is presented and applied to the analysis of timing and signal gain mismatch in the AMUX setup. Typical ENoB versus frequency characteristics were identified and utilized to speed up ENoB simulations and to develop calibration procedures for the different mismatch types in the AMUX setup. The results of the analysis and the performance of the AMUX in the calibrated setup were proven by measurement results.

One of the main directions in the development of optical communication systems is associated with the use of optical fiber (ОF) for data reception and transmission. Therefore, manufacturers began to pay special attention to the creation of new brands of OF, improving their optical and operational characteristics. This makes it possible to improve existing optical fiber components that use OF as an active medium. The most widely used are two-wavelength 1 × 2 WDM multiplexers/demultiplexers designed to separate and combine optical carriers with wavelengths of 1310 and 1550 nm, corresponding to the second and third transparency windows of quartz OF. It should be noted that multiplexers and demultiplexers are the same optical devices, which are spectrally selective splitters. Such devices are distinguished by a sufficiently high level of optical characteristics at a relatively low cost of products. However, an analysis of the multiplexers produced in recent years shows that the characteristics of these devices do not sufficiently correspond to the set of modern requirements imposed by most system developers, in particular on permissible values of external influencing factors, insertion loss and the value of optical isolation of channels. Therefore, the development and research of WDM multiplexers with improved optical characteristics is relevant. One of the possible ways of optimizing such devices using new types of OF with resistance to bending losses, of which WDM multiplexers could be made. In this paper, we consider the possibilities of realizing fused single-mode multiplexers/demultiplexers based on combined fiber structures. The technology and equipment for the manufacture of these devices are presented. The optical characteristics of experimental samples of WDM multiplexers are investigated. The results of testing for the effect of temperature are given.

This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) voltage-mode transmitter (TX) with a four-tap feed-forward equalizer (FFE). A two-step coarse-/fine-tuning technique is adopted in the voltage-mode FFE to reduce the number of front-end slices while maintaining sufficient resolution. In addition, the device sizes in the preceding multiplexer (MUX) and predriver can be enlarged, relaxing the self-loading effect from the layout and improving the bandwidth. An analog impedance control loop is applied to achieve output impedance matching and maintain the corresponding weighting between coarse- and fine-FFE stages. The quarter-rate 4:1 MUX incorporates an automatic phase alignment technique to eliminate the timing constraint. As a result, all of the retiming latches can be removed, saving significant power. Designed and fabricated in 40-nm CMOS, the PAM-4 TX demonstrates a high-quality eye diagram at 112 Gb/s with 3.89-pJ/b energy efficiency under a chip-on-board assembly with 5.5-dB Nyquist loss.

In this modern era, optical technology is used for high-speed processing because photon carries information instead of an electron. In signal processing, multiplexing and demultiplexing are the most valuable component. In this communication, designs of frequency encoded 2:1 multiplexer and 1:2 demultiplexer with the use of Reflective Semiconductor Optical Amplifier and add/drop multiplexer are devised. These proposed designs work at high-speed due to the high speed switching property of reflective semiconductor optical amplifier. In the multiplexing and demultiplexing system, coded data signals and coded control signals are the most important issues. Here, frequency encoding is opted because frequency is unaltered after reflection, refraction, absorption, etc., and it gives a very good response for long-distance transmission of processed data. The operation of devised designs has also been verified through MATLAB Simulink (R2018a) software.

Performance of wavelength division multiplexing (WDM) system mostly depends on the components used in it. Optical add-drop multiplexer (OADM) is one of the most important and widely used components in WDM system used to add or drop the signals. Various types of crosstalk occurred due to the imperfections of OADM affect the WDM system performance. It is important to develop the low crosstalk or crosstalk free OADM to enhance the system performance. In this paper, we have developed an efficient OADM with low incoherent crosstalk based on coupler using isolators and Fiber Bragg Grating (FBG). We have also derived the analytical expressions for bit error rate (BER), relative intensity noise (RIN) and power penalty. It is also observed from the results that the proposed OADM has shown the better performance with lower BER and lower power penalty than the existing models while the performance of the WDM system can increase significantly.

This paper demonstrates a hardware encryption algorithm that can be integrated directly with sensors on the same chip. In contrast to using power-hungry microprocessors and software implementations, the encryption algorithm was based on a Lorenz chaotic system and was implemented as time scaling chaotic shift keying (TS-CSK). The coupled differential equations of TS-CSK were implemented using low power integrators, multiplexers, switches, and passive components. Both a single-ended and differential system was developed. The single-ended based system showed no oscillation, while the differential based system demonstrated oscillation. Experimental measurements of the differential system with an integrated temperature sensor demonstrated the ability to encrypt and decrypt the transmitted signal. The differential encryption/decryption system was implemented in 180 nm technology and operated with a 1.8 V power supply and 1.5 mW of power.

This article proposes the thermometer code converter, which eliminates the requirement of binary code converter to generate gray codes in different digital modulation techniques like pulse code modulation. The nanoscale faster low-power circuit for these thermometer code-to-gray code converter has been achieved with quantum-dot cellular automata (QCA). The proposed converter circuit is made up with new QCA 2:1 multiplexer, which dominates the other existing designs in terms of QCA cells and device density. The circuits are evaluated based on area and operating speed. The design consistency is verified through theoretical values. The dissipated energy explores that the designs have lower energy dissipation. Stuck-at-fault effect analysis on the circuits has been performed. Besides, defect analysis caused by single missing cells, single extra added cells and misplaced cells is also explored. Test vectors are proposed to achieve 100% defect coverage. As encoders, these circuits can be widely employed in those high-performance functions that impose extraordinary design constraints with respect to high frequency, minimal area and low energy consumption.

This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser po...

Today, we are evident to the revolution of the automotive industry and its demand for high bandwidth sensor fusion. Multiple high bandwidth sensors are connected, generating tremendous amount of data to be transferred in real-time in harsh environment, i.e., multi-gigabit intra-vehicle networks. Plastic optical fiber (POF) is an attractive medium for these multi-gigabit intra-vehicle networks due to its inherent EM compatibility, galvanic isolation, low weight, high tolerance to mechanical vibrations, low bending loss, and easy handling. However, commercial off-the-shelf PMMA based POFs are bandwidth-length product limited. Here, we suggest increasing the spectral efficiency using spatial-division multiplexing (SDM). In this article, we have experimentally demonstrated a low cost and eye-safe 3 × 3 multiple-input multiple-output (MIMO) SDM system over a 15 meters multicore (MC) POF using commercial optical components, e.g., RC-LEDs and Si-PIN photodiodes. A 3 × 1 spot-based cores coupler spatial multiplexer was developed to couple the optical components with the MC-POF. This system achieved raw data rates of 1.5 Gb/s and 2.4 Gb/s using offline-processed MIMO equalization. The proposed system enables a flexible and scalable optical MIMO system that can meet the requirements of the automotive industry.

Designing a high-quality switch block ensures the efficient data transmission in digital circuits and systems. In this paper, an innovative 2:1 multiplexer is successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs) at 180 nm SOI technology node. Optimization of the reservoir thickness and gate work function of the S-FED satisfy high ION/IOFF ratio and noise-immunity. DC, AC, and transient mixed-mode simulations are employed to scrutinize and compare performance of constituent logic gates based on the S-FED and CMOS. Simulation results demonstrate superior noise margins up to 100 mV for the S-FED-based inverter compared with the CMOS-based counterpart. Furthermore, the S-FED-based transmission gate with switching frequency of 38.9 GHz can act as a high-speed alternative for the CMOS-based one. Both multiplexer architectures configured by the S-FED and CMOS are compared in terms of performance parameters. In this regard, average power consumption and PDP quantities for the S-FED-based multiplexer reveal significant reductions by about 2 and 3 orders of magnitude, respectively, compared with the CMOS-based one. In addition, propagation delay time increases drastically with scaling power supply in the CMOS-based multiplexer; while, this increase is suppressed for the S-FED-based version.

The approach to designing digital circuits using three-dimensional (3D) perpendicular nanomagnetic logic (pNML) is thoroughly investigated. Nanomagnetic logic (NML) technology eventually optimizes the circuit performance in comparison with conventional metal–oxide–semiconductor (MOS) technology, which suffers from the hot carrier, velocity saturation, and short-channel effects, which may considerably degrade device performance. In contrast, nanomagnetic logic is immune to radiation; it behaves as nonvolatile memory and shows zero leakage current, as required for use in high-speed and low-cost nanoelectronics applications. In this paper, novel and organized designs, e.g., for 3D Ex-OR, parity generator, parity checker, multiplexer, and arithmetic logic unit (ALU) functionality, are synthesized using pNML technology. Previous designs are not compact in terms of delay, layer count, or bounded area. To overcome this, new designs for the mentioned functionalities are proposed based on pNML with smaller area and lower latency compared with previous circuits.

Waveguide components have been widely explored for several decades, due to their inherent merits of low insertion losses, high quality ( Q ) factors, and a significant power-handling capacity. Historically, cavity-based narrowband filters and multiplexers have been explored and designed for base stations and satellite applications. Compared with using single-mode resonators (SMRs), the implementation of multiple-mode resonators (MMRs) in waveguide structures is a promising solution to dramatically reduce the circuit volume and improve the frequency selectivity. Taking advantage of MMR techniques, various innovative waveguide structures have been proposed for a wide range of application scenarios. This article presents an overview of advances in microwave multiple-mode waveguide components, including narrow-, wide-, and multiband filters; multiplexers; three-state diplexers; crossovers; and balanced/unbalanced elements. Representative examples and their results are comprehensively discussed and summarized.

In this article, a beyond 1.6 Tb/s net rate pulse amplitude modulation (PAM) communication system is experimentally demonstrated for 20 m rack-rack optical interconnects with low cost intensity modulation direct detection (IM-DD) architecture, which is enabled by mode division multiplexing (MDM) and wavelength division multiplexing (WDM). The MDM with three linearly polarized modes is realized by a multiplane light conversion (MPLC) mode multiplexer with the maximum modal crosstalk less than – 20 dB. The experimental results show that 2.01 Tb/s (1.84 Tb/s net rate) PAM-6 signal carried on three modes and four wavelengths is successfully transmitted over 20 m standard OM2 multimode fiber (MMF) with the BERs of received signals from all channels below hard decision forward error correction (HD-FEC) threshold of 3.8 × 10–3. Look-up table (LUT) pre-distortion and Volterra nonlinear equalizer (VNLE) are employed for nonlinear impairment mitigation to improve the system performance. Compared to linear feedforward equalizer (FFE), 0.3 dB and 1 dB receiver sensitivity improvements are obtained by LUT and VNLE, respectively. To the best of our knowledge, our proposed scheme achieves the highest bit rate of 167.5 Gb/s per wavelength in MDM system with IM-DD structure. The experimental results show that our proposed PAM MDM communication scheme is a promising candidate for future 1.6 Tb/s short reach rack-rack optical interconnects.

Full adder cell is an important module in arithmetic and processing systems whose performance has a great impact on performance of the whole system. By continuous scaling of the MOS transistors, some challenges and problems appear such as high leakage dissipation for which emerging technologies have been studied as a solution. Carbon nanotube field effect transistor (CNFET) is one of the most potential alternatives for the traditional MOSFET. The threshold voltage of a CNFET can be adjusted by tuning its CNT diameter. This property makes them to be appropriate for designing voltage mode multi-valued logic circuits. In this paper, a novel multiplexer-based ternary full adder cell using CNFET is presented. The proposed circuit is simulated and compared with the state-of-the-art designs using Synopsys HSPICE simulator. Simulations are done to investigate the effect of process (P), voltage (V) and temperature (T) variations on the circuit. The results show that the proposed design reduces the energy consumption by about 54% than the best reported design, while is robust against PVT variations.

Due to the benefits of low power, high bandwidth and complementary metal-oxide-semiconductor (CMOS) compatibility, the design of optical circuits has spurred great attention among researchers in the domain of electronic design automation. With this motivation, all-optical combinational and sequential circuits such as adders, multiplexers, multipliers and flip-flops have been explored in recent times. In this paper, we have explored the designs of all-optical array multiplier and four types of parallel multipliers (carry save adder multiplier, Wallace tree multiplier, Dadda multiplier and reduced area multiplier) using two different design approaches named as Design1 and Design2. In order to design these multipliers, semiconductor optical amplifier (SOA)-based Mach–Zehnder interferometers (MZIs) have been used as the basic optical component. The basic MZI switch, full adder and 2-bit multiplier have been simulated using OptiSystem software to analyze the power loss. Furthermore, an all-optical merged multiplier has been designed, which is often used in digital signal processors. In comparison with other designed multipliers, it is evident from the simulation results that the MZI-based reduced area multiplier of Design1 approach has the highest performance in terms of speed, while the MZI-based carry save adder (CSA) multiplier with Design1 approach has the least optical cost.

Advancements in adiabatic quantum computing have enabled a rapid development in thermodynamically reversible logic circuits, which can reduce energy wastage to almost negligible levels. Various reversible logic gates using silicene-based multiplexer logic devices (SMLDs) are designed and demonstrated herein using Verilog-A, then validated by SPICE circuit simulations. The results confirm that the various reversible gates correctly implement the corresponding truth tables, thereby validating the use of SMLDs as building blocks for such gates. The SMLD-based reversible logic gate designs enable a reduction in hardware complexity by 76.92–80.64% compared with complementary metal–oxide–semiconductor (CMOS) technology and a 50% reduction in hardware compared with pass transistor logic-based designs, respectively.

The objective of this paper is to exemplify the significant improvements achieved in speed and power-consumption by utilizing negative-capacitance Tunnel FETs in sub-0.4 VDD digital logic applications. A heterojunction negative-capacitance TFET (NCTFET) has been designed using SILVACO TCAD and its accuracy demonstrated by properly fitting the simulated polarization data with calculated L-K equation solution. The prospects of the proposed structure have been manifested in the steep average subthreshold-slope of 27mV/decade over 9 decades of current and high ION/IOFF of 1016, possible due to the internal voltage amplification and voltage pinning effects. The device has been suitably implemented in inverter, ring-oscillator, 2:1 multiplexer and Full-Adder circuits and benchmarked in delay and power-consumption with a reference TFET (R-TFET) and previously proposed structures. The effect of varying thickness of ferroelectric material on the circuit-level performance has also been discussed. Furthermore, the NCTFET has been implemented in a 6-T SRAM which successfully demonstrates the effect of tFE on noise margin and read-write delay, operated at 0.4 VDD. The proposed NCTFET has been presented and justified as a promising candidate for high-speed and low power digital circuits.

This paper presents a quad-channel 1.25-10.3125 Gbps wireline transceiver implemented in 40 nm CMOS technology. The transmitter consists of a bit width adjustment, a 40:2 multiplexer, a 2:1multiplexer, and a current-mode logic driver with a 3-tap feedforward equalizer. The receiver has a two-stage continuous-time linear equalizer, a 2-tap half-rate fully adaptive decision-feedback equalizer, a phase interpolation-based digital clock and data recovery (CDR) followed by a 2:40 demultiplexer, a bit width adaption. The transceiver also supports AC/DC coupling, CDR locking detection, PLL locking detection, loss of signal detection, automatic termination impedance calibration. A ring VCO-based PLL is designed in each lane to save power consumption, and a dual-core LC VCO-based PLL is implemented in each bank to generate a low jitter clock signal. At 10.3125 Gbps, the transceiver can equalize 28 dB Nyquist loss at a bit error rate of 10−12, and it consumes 114 mW with a 1.1 V supply. This work presents a high power efficiency of 11.05 mW/Gbps, and the transceiver is suitable for multi-standard applications due to its flexibility and power efficiency.

Suitable techniques for reading out large arrays of metallic magnetic calorimeters are very challenging and demand optimal performance in each system stage to preserve intrinsic fast signal rise time, excellent energy resolution, large energy dynamic range, and highly linear detector response. A multiplexer based on superconducting quantum interference device is the key component in achieving this goal. Linearity of the response requires a technique called flux-ramp modulation, which generates a phase-modulated complex waveform according to the sensor signal. At the end-cap of the signal processing chain it is currently recovered by a demodulation process referred to as Fourier measurement. In this letter, we prove that the mentioned method is equivalent to a maximum likelihood estimation, build an analogy to the sensor array-based direction of arrival estimation, propose an alternative approach based on the eigenvalue decomposition of a correlation matrix, present the mathematical formulation, discuss the results, and compare both methods. Our method is robust against transients due to flux ramp returning point and allows proper estimation in large phase ranges.

Multiplexing and Multiple access technologies are becoming vital components for high-performance wireless communication system. Whereas multiplexing techniques employing either multiple antennas or multiband/wideband antennas for multiplexing are commonly used, these techniques have inherent drawbacks. A feasible solution to this is to employ frequency reconfigurable or frequency agile antennas. This approach has advantages from both multiple antenna and multiband/wideband antenna designs. In this paper, a hardware implementation of a proposed biasing and control circuit/system for wireless multiplexing that utilizes a frequency reconfigurable or frequency agile antenna is reported. The device comprises a microcontroller, DAC, CMOS oscillator, power module and a USB interface for communication with a custom-built software installed on a PC. The device has functions for control, digital signal processing and de-multiplexing. The device is fed with an input multiplexed signal, and the de-multiplexed output signals are extracted and displayed on the graphical user interface of the software. Due to the re-configurability and programmability of the device, it presents a flexible, cost effective solution for a variety of real-world applications.

A semi-active wavelength division multiplexing (WDM) system based on pilot-tone relay detection is proposed and experimentally demonstrated for 5G centralized front-haul network, which is composed of a passive WDM multiplexer at active antenna unit (AAU) side, an active WDM equipment at distributed unit (DU) side, and several WDM optical modules in AAU and DU, respectively. In this semi-active WDM scheme, WDM technology is applied as an optical transport layer to save fibers and the semi-active architecture based on pilot-tone modulation is capable of flexible deployment with lite operation, administration and maintenance (OAM) functions. The experimental results show that the sensitivity penalty is lower than 0.3 dB and the extinction ratio is still higher than 4.2 dB by using 4 % amplitude depth of pilot-tone modulation. The bit rate of the OAM signal is 1024 bps to reuse the existing micro-controller unit in the optical modules for generating and detecting OAM signals. The robustness of the pilot-tone signals is further demonstrated as the sensitivities of the 25-Gbps eCPRI signals and the 1024-bps OAM signals are −16 dBm and −23 dBm, respectively. Compared with the OAM demodulation both in upstream and downstream direction for the active WDM equipment, the number of OAM demodulation unit can be reduced by 50% and the sensitivity requirement of OAM demodulation can be improved by 11.5 dB by using only downstream OAM demodulation unit. Error-free 24-hour transmission of real-time 12-channel 25-Gbps eCPRI signals combined with 1024-bps pilot-tone OAM signals over 10-km single mode fiber is obtained.

This paper highlights a comparative analysis of eight diverse techniques for 2 to 1 multiplexer implementation. The functionality is identical but significant differences in dynamic power consumption and propagation delay are observed. This paper aims to enable the designer to pick out the best fit structure for a specific application in keeping with their design requirement. The multiplexers are designed at 90 nm technology node and simulated at a supply voltage of 1V.

In this work, a device capable of acting as a multiplexer (MUX) and demultiplexer (DEMUX) for electromagnetic waves in gigahertz range is designed and modeled numerically. The device is based on optimized dielectric periodic structures. It can combine signals of different central frequencies injected at its input ports to a single output port, thus acting as a MUX. Reciprocally, the device can separate mixed signals of different frequencies to specific output ports, acting as a DEMUX. To this aim, specific imperfections are introduced into the periodic structure. The design and analysis of the device are performed using the finite-difference time-domain method (FDTD). Transfer functions between pairs of input and output ports are calculated and used to define the design metrics

This paper presents a design method of four-port microstrip filter circuits that have increased filter passbands for multiplexer operation using a simple feed structure. The proposed circuits can be used as different diplexers or even triplexers according to different application requirements. The stub-loaded resonator is used as the basic element to design each filter channel. A simple feed structure with asymmetrical U-shaped feedlines is deployed using the discriminating coupling method. As a result, for each filter channel, specific transmission zero is introduced in other channel frequency bands, thus achieving high channel isolation. Firstly, a compact four-port filter circuit is proposed with four diplexer functions. By exciting one port as the input while two adjacent ports as the output, two filter passbands can be utilized for duplexing channels. Then, without adding extra ports, a four-port five-passband filter circuit is designed. It features a high integration level since it can be used as either diplexers or triplexers, once the corresponding ports are excited. For proof of concept, two design examples are fabricated. The prototypes show good agreement between the simulated and measured results, verifying the feasibility of the proposed design methodology. In addition, the operating frequency and bandwidth of each filter passband can be tuned to desired values. These characteristics are promising in multi-band base-station antenna array feed systems.

A binary comparator architecture is proposed in this work for static logic to achieve both low-power and high-performance operations. It also presents a detailed timing performance and power analysis of various state-of-the-art comparator designs. The main advantages of this design are its high speed and power efficiency maintained over a wide range of operands size, which is useful at low-input data activity environments. The proposed circuit design uses minimum fan-in and fan-out logic gates for achieving high speed and low power dissipation. Utilizing a 2-bit binary comparator circuit with minimum fan-in and fan-out of logic gates (NAND-NOR), the architecture of a parallel binary comparator is proposed for higher input operands by using a low radix multiplexer and priority encoder. Further, to decrease the size of the multiplexer and priority encoder by two times, a general architecture is also proposed by using a 4-bit binary comparator to reduce its complexity. The proposed circuits are optimized in terms of the power consumption and delay, which are due to low load capacitance, low leakages, and reduced dynamic power dissipation. Each of the proposed circuits has its own merits in terms of speed, power consumption, Power-Delay Product (PDP). Its synthesis is done on 180 nm as well as 90 nm CMOS technology using the Cadence tool. The physical layout of the proposed architecture using a 90 nm CMOS process (GPDK process) is also obtained.

Quantum-dot Cellular Automata (QCA) technology is a promising alternative nano-scale technology for CMOS technology. In digital circuits, a multiplexer is one of the most important components. In this study, an efficient and single layer 2 to 1 QCA multiplexer circuit is proposed using majority gate and inverter gate. In addition, efficient 4 to 1 and 8 to 1 QCA multiplexer circuits are implemented using this 2 to 1 multiplexer circuit. The developed multiplexer circuits are implemented in QCADesigner tool. According to the results, the developed 2 to 1, 4 to 1, and 8 to 1 multiplexer circuits utilize 16 (0.01?m2), 96 (0.11?m2), and 286 (0.43?m2) QCA cell (area). The results demonstrate that the proposed 8 to 1 multiplexer circuit reduces the cost by about 25%- 99% compared to the existing multiplexer circuits.

A multifunctional molecular logic system based on the differential fluorescence readouts at three wavelengths, 415, 480 and 550 nm, with singular excitation at 360 nm in the course of the two-step energy transfer cascade between three readily available standard fluorophores, coumarin 1 (Cou1), curcumin (Cur) and rhodamine 123 (Rh123) has been reported here, avoiding the multi-step synthetic reactions. The logic functionalities of all four single-input–single-output logic gates, all sixteen dual-input–single-output logic gates, a number of combinational logic gates (half-adder, half-subtractor, 2 : 1 multiplexer, 1 : 2 demultiplexer, 4-to-2 encoder and 2-to-4 decoder), and logically reversible Feynman and transfer gates have been executed on this molecular system. The logic outcome could be effortlessly switched through the whole array of all-photonic logic gates simply with the switching of chemical inputs and optical outputs under singular 360 nm excitation. The approach towards the multifunctional opto-chemical logic system is quite simple and it is a generalized method based model that should work well with other sets of fluorophores supporting multi-step excitation energy transfer. Versatile logic functioning and their effortless switchability on this molecular system would certainly contribute to the silico-mimetic molecular logic research as an alternative for putting together and interconnecting different gates to fabricate molecular integrated circuits (MICs).

Reconfigurable optical add-drop multiplexer (ROADM) is one of the key building blocks for on-chip optical networks, which can download the desired signals from the bus waveguide to the corresponding drop port and upload the local signals from the add port to the bus waveguide to achieve the signals dropping/adding between the local and the bus waveguide. In this letter, we propose a ROADM based on a Benes network for mode-division multiplexing systems. As a proof of the concept, a ROADM with three quasi-transverse electric modes (TE0-TE2) is fabricated and experimentally demonstrated, which can download signals from TEi (i = 0, 1, 2) mode channel in the bus waveguide to an arbitrary local drop port or upload local signals to TEi mode channel via an arbitrary add port. The excess loss of the fabricated device is less than 10.7 dB, and the crosstalk among different space or mode channels is lower than −13.7 dB. Finally, a 12 Gbps data transmission experiment is carried out to verify the performance of the device. The proposed device is reconfigurable and scalable, and thus, it is expected to be used for optical data processing in the mode-division multiplexing systems.

The results of investigation of the spectral characteristics of some passive fiber-optic components, such as optical isolators, circulators, spectral filters and multiplexers, used in quantum key distribution (QKD) systems and contributing to the protection of QKD system from active optical probing attacks are presented. An assessment of the required degree of isolation is also given, which ensures reliable protection of the QKD system against Trojan-horse attacks under the most stringent conditions for legitimate users. Based on the formulated requirements and measurement results, the effectiveness of protection using the investigated passive insulating components is analyzed. Using the example of calculating the insulation for the QKD system scheme presented in the work, the achievement of the required level of isolation (150 dB) in the entire considered spectral range is shown.

A full-duplex self-recovery optical fibre transport system is proposed on the basis of a novel passive single-line bidirectional optical add/drop multiplexer (SBOADM). This system aims to achieve an access network with low complexity and network protection capability. Polarisation division multiplexing technique, optical double-frequency application and wavelength reuse method are also employed in the transport system to improve wavelength utilisation efficiency and achieve colourless optical network unit. When the network comprises a hybrid tree–ring topology, the downstream signals can be bidirectionally transmitted and the upstream signals can continuously be sent back to the central office in the reverse pathways due to the remarkable routing function of the SBOADM. Thus, no complicated optical multiplexer/de-multiplexer components or massive optical switches are required in the transport system. If a fibre link failure occurs in the ring topology, then the blocked network connections can be recovered by switching only a single optical switch preinstalled in the remote node. Simulation results show that the proposed architecture can recover the network function effectively and provide identical transmission performance to overcome the impact of a breakpoint in the network. The proposed transport system presents remarkable flexibility and convenience in expandability and breakpoint self-recovery.

Monolithic 3-D (M3D) integration offers higher-density integration compared to 3-D integration based on through-silicon vias. Advances in testing are however needed to screen defects in M3D integration without significantly impacting manufacturing cost. We propose a built-in-self-test (BIST) solution to target shorts and opens in interlayer vias (ILVs). In the proposed solution, scan cells at the interface of two layers are stitched into a twisted-ring counter (TRC) using their functional outputs and ILVs. The interface-register cells launch and capture tests, and a test path consists of ILVs and a multiplexer. We map the problem of minimizing the length of the wires added to stitch the TRC to that of finding a minimum-cost Hamiltonian circuit in a weighted bipartite graph. Since the weighted Hamiltonian circuit problem is NP-Complete, we propose a heuristic algorithm for this problem. We also propose a framework based on artificial neural network to carry out diagnosis when a chip fails the proposed test. We show using simulations that the proposed BIST solution can detect all opens and shorts. We also show using simulations that the proposed diagnosis framework can accurately estimate the size of defects in ILVs.

Integrated photonics offers attractive solutions for realizing combinational logic for high-performance computing. The integrated photonic chips can be further optimized using multiplexing techniques such as wavelength-division multiplexing (WDM). In this paper, we propose a WDM-based electronic–photonic switching network (EPSN) to realize the functions of the binary decoder and the multiplexer, which are fundamental elements in microprocessors for data transportation and processing. We experimentally demonstrate its practicality by implementing a 3–8 (three inputs, eight outputs) switching network operating at 20 Gb/s. Detailed performance analysis and performance enhancement techniques are also given in this paper.

We describe the principle, design, and prototyping of a free-space-optics-based core selective switch (CSS) for spatial channel (SCh) networks (SCNs) in the age of space division multiplexing (SDM). A CSS in an SCN corresponds to a conventional wavelength selective switch (WSS) in a current wavelength division multiplexing network. It incorporates functionalities for spatially demultiplexing SChs from an input SDM port and for switching and multiplexing any of them into any of output SDM ports. We discuss the design for free-space-optics-based CSSs that is applicable to CSSs supporting various numbers of cores per multicore fiber (MCF) and various numbers of MCF ports. We show an example of an implemented 5-core 1 × 6 CSS prototype that integrates an MCF collimator, spatial multiplexer/demultiplexer array, and liquid-crystal-on-silicon spatial light modulator. Although some output MCF ports exhibit relatively high insertion loss (IL), the CSS prototype shows that a CSS will potentially provide low net IL at the level of approximately 2 dB. To verify that there are no unknown deteriorating factors in the CSS prototype, we tested the prototype implemented in a hierarchical optical cross-connect configuration by measuring the pre-forward error correction bit error rate. Spatial bypassing and spectral grooming of a 900-Gb/s SCh employing a CSS-based spatial cross-connect and a conventional wavelength cross-connect are successfully demonstrated with no optical signal-to-noise ratio penalty.

A major challenge in spectrum sensing for cognitive radio (CR) applications is the very high sampling rates involved, which imposes significant demands on the signal acquisition technology. This has given impetus to applying compressive sensing (CS) as a sub-Nyquist sampling paradigm for CR-type wireless signals which exhibit sparsity in certain domains. CS architectures like the random demodulator (RD) and compressive multiplexer (CM) can be used for CR spectral sensing, though both are inherently restricted in terms of the signal classes they can effectively process. To address these limitations, this paper presents two unified RD and CM-based CS architectures that seamlessly integrate precolouring and the multitaper spectral estimator into their respective structures to facilitate efficient sensing of both digitally modulated and narrowband signals, along with popular CR-access technologies like orthogonal frequency division multiplexing. A significant feature of these unified CS architectures is they do not require a priori knowledge of either the input signal or modulation scheme, while a tristate spectral classifier is introduced to afford notably enhanced spectrum access opportunities for unlicensed secondary users. A critical performance evaluation corroborates that both unified architectures demonstrate consistently superior CS results and robustness across a broad range of CR-type signals, modulations and access technologies.

To combine the individual benefits of probabilistic-shaping (PS) and time-frequency-packing (TFP), we consider for the first time PS-TFP wavelength-division multiplexing (WDM) superchannels. However, TFP introduces inter-symbol interference (ISI) and/or inter-carrier interference (ICI). Moreover, the presence of reconfigurable optical add-drop multiplexers in the fiber links may further degrade the system performance. In this letter, we efficiently handle such challenges to present PS-TFP superchannels enabling Terabit-per-second data rates. For this, we perform a joint ISI and ICI channel estimation in tandem with turbo equalization to mitigate the interference. We investigate optimizing the parameters in the shaping and packing dimensions to achieve a desired target spectral efficiency. We show through our numerical results that such an optimized PS-TFP transmission leads up to 1.2 dB performance improvement over an unshaped Nyquist WDM system under similar conditions.

A cascaded Mach-Zehnder interferometer based filter for coarse wavelength (de)multiplexing (CWDM) at the O-band is fabricated and tested on a silicon nitride on SOI platform. We characterize the chip-to-chip performance variability of the filter devices on a wafer. Using the optical measurement data, we apply Bayesian inference methods to estimate the waveguide geometery parameters and also quantify the uncertainty of the estimates.

Purpose Owing to recent challenges of CMOS manufacturing and power consumption in silicon technologies among alternative technologies, Nanomagnetic logic (NML) is one of the most promising technologies, so it was selected for this study. NML is non-volatile with ultra-low power dissipation that operates at room temperature. This paper aims to propose novel implementation of 2% and 4% multiplexers (MUXs) in NML technology. Design/methodology/approach The proposed multiplexers in NML technology are verified by HDL-based simulators. In addition, this study estimated area and power dissipation of the proposed design to compare and approve the promising improvements in comparison to other similar NML implementations. Findings The results show the remarkable improvements in terms of APDP term in comparison to the recent proposed MUXs in NML technology which are reported in Table 2. The proposed implementation of the MUX in NML is designed in three-dimensional layout to improve interconnection complexity which is an integration challenge. Also, by facilitating the routing signals and total wire length needed for clock signals, the negative impact of the power dissipated in clock wires is improved. Originality/value These findings would appeal to a broad audience, such as the readership of Microelectronics International Journal. The authors confirm that this work is original and has not been published elsewhere nor is it currently under consideration for publication elsewhere. All authors have approved the paper and agreed with submission to Microelectronics International Journal. The authors have read and have abided by the statement of ethical standards for manuscripts submitted to Microelectronics International Journal. The authors have no conflict of interest to declare.

This article presents a 50–112-Gb/s current-mode four-level pulse amplitude modulation (PAM-4) transmitter with a two-tap fractional-spaced feed-forward equalizer (FFE). The principle analysis shows that the fractional-spaced FFE can provide an extended compensation range beyond the Nyquist frequency without amplifying noise. For the transmitter prototype implementation, the tap delay is adjusted by a coarse–fine capacitor array-based delay cell located in the quarter-rate clock path. Dynamic latches, pseudo-AND2s, and bandwidth-enhanced 4:1 multiplexers are employed to guarantee an adequate timing margin and a sufficient bandwidth for the data rate of 112 Gb/s. A linearity-optimized FFE driver is employed to overcome the current compression caused by the channel-length modulation. Fabricated in a 65-nm CMOS process, the measurement results show that the proposed fractional-spaced FFE can significantly improve the eye-opening in terms of expanding the eye width and optimizing the eyelid thickness. The PAM-4 transmitter can operate in both full-rate PAM-4 and half-rate NRZ modes, achieving a maximum data rate of 112 Gb/s with an energy efficiency of 2.17 pJ/bit.

Reconfigurable logic and neuromorphic devices are crucial for the development of high-performance computing. However, creating reconfigurable devices based on conventional complementary metal–oxide–semiconductor technology is challenging due to the limited field-effect characteristics of the fundamental silicon devices. Here we show that a homojunction device made from two-dimensional tungsten diselenide can exhibit diverse field-effect characteristics controlled by polarity combinations of the gate and drain voltage inputs. These electrically tunable devices can achieve reconfigurable multifunctional logic and neuromorphic capabilities. With the same logic circuit, we demonstrate a 2:1 multiplexer, D-latch and 1-bit full adder and subtractor. These functions exhibit a full-swing output voltage and the same supply and signal voltage, which suggests that the devices could be cascaded to create complex circuits. We also show that synaptic circuits based on only three homojunction devices can achieve reconfigurable spiking-timing-dependent plasticity and pulse-tunable synaptic potentiation or depression characteristics; the same function using complementary metal–oxide–semiconductor devices would require more than ten transistors. A homojunction device made from two-dimensional tungsten diselenide can be used to create circuits that exhibit multifunctional logic and neuromorphic capabilities with simpler designs than conventional silicon-based systems.

Testing becomes an inevitable part of the VLSI circuit. All the circuits or products must be verified before delivery. The data collected during testing is used to remove the faulty parts from the products and help to enhance the design and manufacturing process and improve the returns as well. There are several contributions made by researchers which are majorly based on Linear Feedback Shift Register (LFSR), bit swapping LFSR and dual threshold bit swapping LFSR methods. Reduction of delay, power consumptions and fault coverage are considered as major factors from the above methods. The proposed approach uses Bit Swapping-Linear Feedback Shift Register (BS-LFSR) architecture which integrates pre-charge, set-reset and gate replacement with mux techniques have alleviated the inherent drawbacks of linear feedback shift register and produced better results. Pre-charge method is reducing the delay and power consumption there by maximizing the operating frequency angle with high performance. High fault coverage is achieved through set and reset technique. Multiplexers mainly employed to minimize the delay and power consumption. BS-LFSR pattern generators are used to decrease the transition power from high switching action. These are producing an arbitrary test sequences with less power of switching by determining the pretense space between two subsequent designs. The area is reduced with the help of combinational logic. Experimental evaluation is done using ISCAS89 benchmark datasets. From the results, it is inferred that the fault coverage is increased and power consumptions are reduced.

Quantum-dot cellular automata (QCAs) are one of the most significant state-of-the-art technologies that have exhibited the potential to replace the complementary metal oxide semiconductor. QCA offers a variety of benefits over its conventional counterpart, including size, latency, and energy consumption. Meanwhile, multiplexers are crucial to the design of arithmetic and logic circuits, and NOT-AND (NAND) gates are universal gates that allow the design of any circuit. In this paper, we propose a new multiplexer based on three NAND gates in QCA. De Morgan's law is used to derive new equations and to design multiplexers using only NAND logics. The proposed circuit is designed and verified not only to minimize time and space complexity but also to minimize energy loss. Finally, we design an arithmetic circuit that is capable of performing various operations using the proposed multiplexer.

A 50-Gb/s four-level pulse-amplitude modulation (PAM4) silicon photonic transmitter is presented, which is composed of a 40-nm bulk CMOS driver hybrid integrated with a 180-nm silicon-on-insulator (SOI) CMOS Mach–Zehnder modulator (MZM). To recover and demodulate 50-Gb/s PAM4 data into dual-25-Gb/s nonreturn to zero (NRZ) streams for the co-designed MZM digital-analog converter (DAC), a reference-less clock and data recovery (CDR) is integrated, and to achieve high swing and high speed, the driver is made in a distributed amplifier (DA), employing push–pull cells that are grouped in three segments. A digital-assisted distributed driver (DADD) that replaces the input T-line by segmented 2:1 multiplexers and buffers is, thus, proposed. Precise time gating in each segment allows for velocity match in both the DA and optical DAC, as well as the in-segment pre-emphasis without power-hungry analog delay stages. Measurement results show that the driver and CDR achieve 4-VPP differential swing, 1.19-ps rms jitter, and 1.34-W power consumption at 50 Gb/s. An optical transmitter is demonstrated by wire-bonding the driver to the MZM DAC, achieving 50-Gb/s PAM4 output with 6.35-ps rms jitter and improved linearity.

In Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM), the most commonly used timing scheme for conventional Voltage-mode Sense Amplifier (VSA) is the global activated timing. Obviously this method cannot obtain the optimal yield because different bit-cells have its sensing latency respectively. This paper proposes a self-timed voltage-mode sense scheme named ST-VSS which can enable optimal timing depending on the bit-cell discharging ability. Two circuit structures are proposed: The single SA structure uses a multiplexer at the input of the SA. Its successive sensing operations are implemented with input offset flipping. A dual SA structure is reconfigured by built-in-self-test (BIST) method to the opposite offset states to monitor sensing results from each other. The sensing operation can be immediately terminated after successful reading. The proposed ST-VSS is applied to a 32bits/word MRAM using 28-nm CMOS process. Simulation results show that the successful sensing rate across a wide range of voltages can be improved, comparing with the conventional scheme. The single SA structure obtains 32%~42% yield improvement, costs 44.1%/26.9%/19.3% energy, and brings 8.3%/5.8%/2.9% layout area penalty in 128/256/512 column depth, respectively. The dual SA structure gets 54%~65% yield improvement, costs 66.2%/38.6%/27.5% energy, and brings 26.4%/13.8%/7.1% area penalty in 128/256/512 column depth conditions, respectively.