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A 4th-Order Wideband Sigma Delta modulator structure is proposed in this paper, which uses linear system theory technique. There are many implementation techniques to improve the performance of Sigma Delta ADCs, such as noise coupling, differential sampling and dynamic elements matching. An extra loop delay is needed to be added in the system. This paper explains how to make the modulator stable with the addition of feed-forward and feed-back branches which are used to compensate the extra loop delay. Next, we restore the signal and noise transfer functions. A 4th-Order Wideband deltasigma modulator have been designed and simulated to verify the method.

A 4th-Order low-distortion low-pass ΣΔ modulator structure is proposed in this paper, which uses the timing-sharing between the 3rd and 4th integrators during one clock phase. Compared with conventional cascade of integrators with distributed feed-forward (CIFF) sigma-delta modulator structure, the proposed structure not only solves the critical timing issue for the quantizer and feedback DAC path, but also eliminates an extra active adder to sum up the input feed-forward. By methods of delay redistribution structure, the time for quantization and feedback dynamic element match (DEM) operation can be extended from a non-overlapping interval for a conventional low-distortion structure to half of the sampling clock period. Capacitive input feed-forward (CIF) methodology eliminates the adder in front of the quantizer. Further, the op-amp of the last integrator is used as an active adder by op-amp sharing. Therefore, the power consumption can be reduced and the linearity of the feedback DAC is improved because of the increasing time which used for implementation of DEM algorism. The proposed 4th-Order low-distortion low-pass ΣΔ modulator with 4-bit quantizer is simulated in MATLAB. From the simulation results, the proposed structure can achieve a peak SNR (signal- to-noise ratio) of 87dB with 2.5MHz bandwidth under 32 oversampling ratio at 160MHz sampling frequency and the ENOB of 14.234bits in non-ideal condition.

This paper presents a design and analysis method of a bandgap reference circuit. The Bandgap design is realized through the 0.18um CMOS process. Simulation results show that the bandgap circuit outputs 1.239V in the typical operation condition. The variance rate of output voltage is 0.016mV/°C? with the operating temperature varying from-60°C? to 160°C?. And it is 3.27mV/V with the power supply changes from 1.8V to 3.3V.

Based on requirements on high performance and high resolution of modulators, a fourth-order Sigma-Delta modulator for audio application is developed in this paper. The modulator is designed under the commercial 0.5μm CMOS process and the circuits are given simulations by Spectre. The sampling frequency of sigma-delta modulator is 11.264 MHz, and OSR is 256 within the 22 kHz signal bandwidth. Measure performance shows that Sigma-Delta modulator enables its maximum SNR to achieve 103.5dB, and the accuracy of Sigma-Delta modulator is up to 16 bit.

This paper presents the design of low noise CMOS pre-amplifiers based on photoelectric detection systems, which can directly affect the detecting precision of the whole systems. The design of pre-amplifier circuit from photoelectric detector was introduced. The photoelectric conversion circuit, amplifier circuit bandwidth, amplifier circuit noise, amplifier circuit stabilization and other questions were mainly discussed, and an amplifier circuit capable of effectively decreasing the noise, the temperature drift and a large dynamic range was designed. This paper analyzes the sources of photoelectric detection circuit internal noise, and gives the formulas of internal noise, designs a variable equivalent load photoelectric conversion circuit, and is verified by experiments. Then the result is used to reduce the noise of CMOS based operational amplifiers and finally implement the design work of pre-amp using 0.5μm CMOS Technology.

This paper presents a photoelectric detection circuit for microfluidics chip. The proposed photoelectric detection system can reduce noise and increase sensitivity. It is consist of pre-amplifier, ac-amplifier and band-pass filter. The transfer function of photoelectric detection circuit is introduced. The circuit implementations and simulation results are given. The proposed photoelectric detection circuit is suitable for integrated microfluidics chip.

This paper presents a micro-displacement sensing circuit, which can detect sensing capacitors of levitated rotor. To ensure the high resolution, noise analysis of pre-amplifier of micro-displacement sensing circuit is conducted. The results show that choosing low noise amp and decreasing Cf /C1 can reduce the electronic noise.

This paper presents a complete set of SIMULINK models, which allow exhaustive behavioral simulations of fluxgate system to be performed. The model construction is detailed and it is applied to the Vacquier-type fluxgate sensor. Well known characteristics of these sensors are confirmed through the simulations. In spite of this simplicity, the model has been successfully used to describe the variation of the output of a Vacquier-type fluxgate sensor with the amplitude and the frequency of the driving current. Using a previously developed 2nd harmonic fluxgate magnetometer, some preliminary experimental results are obtained confirming the appearance at its output.

A low power CMOS instrumentation amplifier used for biomedical applications is presented in this paper. It consists of a low power operational amplifier with CMFC structure. By analysis and optimization of the parasitic effects and parameters, instrumentation amplifier has better performance in every aspect. This simulation result shows that, in the case of guaranteed bandwidth, the amplifier can suppress flicker noise interference effectively. The instrumentation amplifier designed in 0.5 μm CMOS technology with 3.3 V power supply shows a dynamic range of 70.1 dB and 23.48 ns settling time within 0.05% accuracy. The main amplifier dissipates 10.5mW power. It also includes a bias circuit that dissipates 2.2mW power.

This paper presents a low-power multistage amplifier with a novel Transconductance with Capacitances Feedback Compensation (TCFC) technique. A transconductance stage and two capacitors introduce negative feedback to a three-stage amplifier, which significantly improves the performance such as gain-bandwidth product, slew rate, stability and sensitivity. Implemented in a commercial 0.5-μm CMOS technology and driving 10pF capacitive load, a three-stage TCFC amplifier achieves over 120dB gain, 1.515MHz GBW and 1.3V/μS average slew rate, while only dissipating 380μW under 3.3V supply.

This paper presents a low-power multistage amplifier with a novel capacitor-multiplier frequency compensation (CMFC) technique. The proposed compensation strategy can allow the circuit to occupy less silicon area and to drive large capacitive loads more effectively. Moreover, smaller physical capacitance results in higher gain-bandwidth product (GBW) and improved transient responses. Furthermore, the capacitor multiplier stage (CMS) embedded in CMFC creates a left-half plane (LHP) zero, which boosts the phase margin and enhances the stability of the amplifier. Implemented in a commercial 0.5-μm CMOS technology and driving 500pF capacitive load, a three-stage CMFC amplifier achieves over 120dB gain, 1.699MHz GBW and 1.625V/μS average slew rate, while only dissipating 330μW under 3.3V supply.