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We report on the first non-contact, non-destructive performance measurements of embedded ring oscillators. Measurements are made on inside the die active area as early as metal 1. A 90nm logic CMOS technology was used for this work. We have measured residual across-field performance variation separate from and of opposite sense to wafer uniformity. This effect cannot be extrapolated from scribe measurements

This paper presents a test chip and infrastructure IP (I-IP) solutions to accelerate process development of interconnects on new advanced technology and to improve the back-end-of-line (BEOL) yield on products. The test chip and the I-IP use the same architecture which is described in using a bottom-up approach with emphasis on its scalability. Using this test chip, the specifications of process back-end critical parameters can be quickly and easily analyzed. Using the dedicated infrastructure IP, the defect density tracking as well as the test and diagnosis of process back-end critical parameters can be rapidly and simply performed. To reach this goal, the test flow and its related signature extraction are given. Moreover, each extracted signature is merged in a database which are used to diagnose defected back-end parameters in the I-IP. Thus, the use of the test chip and the I-IP allows us to improve the manufacturing process from the beginning of a new technology development and integration to the end of ramp-up production and product manufacturing.

In this paper, a new method (ARPIC: automatic representation of patterns for interconnect characterization) of interconnect capacitance characterization is shown. ARPIC is a matrix of 1606 patterns containing the most frequent capacitive loads existing in a design. Its main purpose is to calibrate a simulator. A very good fit is obtained between measurements and simulation for a state-of-the-art 0.18 /spl mu/m CMOS process with low-k dielectric, and we demonstrate that the ARPIC method can characterize interconnect capacitance with 0.1 fF resolution.