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1. Block authors, integrators face myriad challenges -- Reuse redraws design job

2. EDA tools

3. EDA & ASICs, coping with complexity: part 2: design re-use

4. Pcb layout integrates signal integrity

6. FPGA retargeting remains elusive

7. Codesign turns workplace on its head

8. Systems-on-silicon designs talk in new languages

9. Upheaval looms for IC design methodologies

10. RTL tools create 'virtual prototype.' (register-transfer-level tools)(Special Report On EDA Tools: Part 2: Design Planning)

11. MEMS the word in auto parts

12. Design worlds take integration route

13. EDA tools

14. The logic-verification crunch

15. EDA tools

16. EDA & ASICs: coping with complexity: part 1: high-level design tools

17. Designer's views mixed on analog HDLs

18. LSI Logic links ASICs to synthesis

19. Patent hearings are eyed by EDA world

20. Major EDA vendors say aye to EDIF

22. Designers yearn for integration

24. Mentor ports 8.0 to four platforms; becoming a software-only vendor

25. Cadence, Valid set to merge

27. EDA leaders feel the pinch

29. Tricky times in EDA: the business is in transition, not trouble

32. Intergraph offers $14M for what's left of Daisy

33. PLD tools moving up

34. Design gears up for future -- Multicore poses multitude of EDA considerations

35. Tool makers look to fix bottlenecks, fill gaps

36. Multiprocessing used to break EDA timing bottleneck

37. Constraints open new EDA standards battleground

38. Low-power IC design techniques may perturb the entire flow

39. IEEE's patent policy fails to quell EDA standards row

40. Design automation -- Synopsys library tools boost CCS models

41. Dearth of tools could stall multicore onslaught

42. Post-silicon fix for IC variability could transform DFM

44. Blaze lights DFM fire in merger with Aprio

45. Fearless predictions for 2007

46. EDA looks to two good years in a row

47. Standards open up EDA arena?

48. EDA growth surges-but will it stick?

49. EDA industry loses an independent voice

50. Designers: Give us single power spec -- Goal is convergence, but EDA vendor rivalry keeps dueling standards in play

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