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In this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design cycle. The modeling is based on a manufacturing (rather than design-manual) description of the back-en d-of- the-line (BEOL) cross section of a given technology and on a full, yet contained, description of the power-ground mesh in which the data bus is embedded. One major. aspect of the resulting electrical models is that they allow the designer to evaluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high- frequency phenomena as the dependence of the current return- path resistance on frequencies. The CAD methodology described in this paper has been extensively correlated with on-chip hard- ware measurements. [ABSTRACT FROM AUTHOR]

In this paper, the self-consistent, frequency-dependent dielectric constant ∊!r@(f) and dielectric loss tan δ(f) of several materials are determined over the range 2 to 30 GHz using a short-pulse propagation technique and an iterative extraction based on a rational function expansion. The simple measurement technique is performed in the time domain on representative printed circuit board wiring. Broadband, fully causal transmission-line models based on these results are generated up to 50 GHz for card wiring using low loss materials including BT, Nelco N4000-13, and Nelco N4000-13SI. Simulation and modeling results highlight the need for the accurate frequency-dependent dielectric loss extraction. Signal propagation based on these results shows very good agreement with measured step and pulse time-do- main excitations and provides validation of the measurement and model generation technique. [ABSTRACT FROM AUTHOR]