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Accompanying with the popularization of portable equipments, and the rapid growth of the size of the electric systems, efficient low power design methodologies have been highly required. To satisfy these requests, a high accurate and high efficient power analysis in higher abstraction level is very important. The design environment is composed by efficient algorithms of power modeling, power library building, and data extracting. Those components of the environment should be balanced for the total efficiency and accuracy. We have proposed a new efficient power modeling environment which uses a look-up table (LUT). It reduces the size of the LUT drastically, compared to conventional algorithms. It makes the power analysis and library building high efficient. The experimental results show that our approach reduces the computation time to build the library to one tenth while keeping the accuracy of the power analysis. The RMS error and the largest error has been less than 8.30%, 59.16%, respectively.

Hydrogenated amorphous silicon carbide films are grown in inductively coupled glow discharge apparatus using hydrocarbon gas of methane series CH 4 , C 2 H 6 , C 3 H 8 and C 4 H 10 mixed with silane and their properties are compared.

Hyperfine structures in ESR that originate from the interface between amorphous semiconductors and insulating substrates are found and discussed.

Using the infrared absorption spectra, ESR, reflectance and transmittance spectra and photoluminescence spectra, the structural and electronic properties of specimens deposited on to low temperature substrates by glow discharge decomposition of disilane and by HOMOCVD of monosilane are discussed.

In a self-diagnosable integrated circuit device comprising sequential circuit elements in an internal logic circuit, a first test pattern signal is successively produced in a test mode from a test pattern generating circuit and stored into the sequential circuit elements with a first timing signal given from a timing signal generating circuit to the internal logic circuit. After storage of the first test pattern signal into the sequential circuit elements, a second test pattern signal is produced from the test pattern generating circuit with a second timing signal given to the internal logic circuit. The internal logic circuit carries out processing operations determined for the second timing signal and produces an output data signal which is dependent on the first and the second test pattern signals and which is evaluated by an external circuit. Storage of the first test pattern signal may be made by forming a scan path through a gate circuit connected to each sequential circuit element. Alternatively, each sequential circuit element may be loaded with the first test pattern signal by assigning addresses to the respective sequential circuit elements and by indicating each address.