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A developed physical model and a simulation algorithm are used to predict electromigration (EM)-induced stress evolution in dual-inlaid copper interconnects. Incorporation of all important atom migration driving forces into the mass balance equation and its solution, together with the solution of the coupled electromagnetics and elasticity problems, allows the simulation of EM-induced degradation in a variety of dual-inlaid copper interconnect segments with different dominant paths for mass transport [V. Sukharev and E. Zschech, J. Appl. Phys. 96, 6337 (2004)]. The results of the numerical simulation have been proven experimentally by EM degradation studies on fully embedded dual-inlaid copper interconnect test structures and by subsequent microstructure analysis, mainly based on electron backscatter diffraction (EBSD) data. The EM-induced void formation and its virtual movement and growth in a copper interconnect were continuously monitored in an in situ scanning electron microscopy experiment. The copper microstructure, particularly the orientation of grains and grain boundaries, was determined with EBSD. It has a significant influence on grain boundary diffusivity and consequently on the mass transport along grain boundaries. For interconnects with interfaces that resist atomic transport and where grain boundaries are the important pathways for atom migration [E. Zschech et al., Z. Metallkd. 96, 996 (2005)], degradation and failure processes are completely different for microstructures with randomly oriented grain boundaries compared with “bamboolike” microstructures. The correspondence between simulation results and experimental data indicates the applicability of the developed model for optimization of the physical and electrical design rules. Simulation-based optimization of the interconnect architecture, segment geometry, material properties, and some of the process parameters can produce on-chip interconnect systems with a high immunity to EM-induced failures. [ABSTRACT FROM AUTHOR]

A physical model and a simulation algorithm are used to predict an electromigration-(EM-) induced void nucleation and growth in dual-inlaid copper interconnect. Incorporation of all important atom migration driving forces into the mass balance equation and its solution together with solution of the coupled electromagnetics, heat transfer, and elasticity problems allows to simulate EM-induced degradation in a variety of dual-inlaid copper interconnect segments characterized by different dominant channels for mass transport. The interface bonding strengths, significantly influencing the interface diffusivity and consequently the mass transport along interfaces, result in completely different degradation and failure pictures for the weak and strengthened copper/capping layer interfaces. Strengthening of the top interface of inlaid copper interconnect metal line is a promising way to prolong the EM lifetime. The results of the numerical simulation have been proven experimentally by the EM degradation studies on the fully embedded dual-inlaid copper interconnect test structures. EM-induced void formation, movement, and growth in a copper interconnect were continuously monitored in an in situ scanning electron microscopy experiment. The correspondence between simulation results and experimental data indicates the applicability of the developed model for optimization of the physical and electrical design rules. Simulation-based optimization of the interconnect architecture, segment geometry, material properties, and some of the process parameters can generate on-chip interconnect systems with a high immunity to EM-induced failures. [ABSTRACT FROM AUTHOR]

This article investigates the effect of grain structure on electromigration (EM) reliability of dual-damascene Cu interconnects with a CoWP capping layer, including the lifetime and statistics. Downstream EM tests were performed on two sets of CoWP-capped Cu interconnects with different grain sizes. Compared to Cu interconnects with the standard SiCN cap layer, the CoWP capping clearly improved the EM lifetime by ~24x for the small grain structure and by another ~14x for the large grain structure. Here, the effect of grain structure on EM lifetime was attributed to the grain boundary contribution to mass transport. The lifetime improvement, however, was accompanied with an increase in the statistical deviation, increasing from 0.27 for the SiCN cap to 0.53 for the small grain structure and to 0.88 for the large grain structure with the CoWP cap. This was attributed to the effect of grain structure in changing the statistical distribution of flux divergence sites and thus the failure statistics. [ABSTRACT FROM AUTHOR]

In situ electromigration experiments were carried out to study electromigration-induced failure in the upper and lower layers in dual-damascene Cu test structures. The observations revealed electromigration-induced void movement along the Cu/dielectric cap interface. It supports the premise that Cu/Si3N4 interface acts as the dominant electromigration path. However, the observed void nucleation occurs in the Cu/Si3N4 interface at locations which are far from the cathode, and void movement along the Cu/Si3N4 interface in opposite direction of electron flow eventually causes void agglomeration at the via in the cathode end. The different electromigration behaviors of the upper and lower layer dual-damascene structures are discussed. [ABSTRACT FROM AUTHOR]

A model has been developed to simulate electromigration degradation in an interconnect segment in two dimensions using finite differences. The model was deployed on a parallel computer to statistically assess the lifetimes. The simulation takes into account the diffusion paths for electromigration mass transport along the grain boundaries and the capping layer. The microstructure is generated with a Monte Carlo algorithm, using a modified Potts model. Diffusivities along the grain boundaries and the capping layers were applied as multiples of a base diffusivity and were statistically scattered. The simulation results correlate well with electromigration tests. [ABSTRACT FROM AUTHOR]