Search

The sensitivity of existing fingerprint sensors (FPSs) can decrease considerably owing to environmental factors and parasitic capacitance. In order to overcome this limitation, this paper proposes a highly-sensitive 300 dpi mutual-capacitive transparent fingerprint sensor (FPS) with uniquely designed reference lines for device security. Specifically, the reference lines of the FPS induce capacitance cancellation. Images of fingertips under dry, wet, and oily surface conditions were obtained in the presence and absence of the reference lines. The results showed that the fingerprints were significantly distorted in anomalous surface environments when the reference lines were not used. However, when the reference lines were used, the sensitivity improved irrespective of the environmental conditions. With the edge-detection processing, the proposed FPS exhibited 9.25 %, 61.49 %, and 8.60 % increase in the ridge sensing improvement (RSI) of dry, oil, and wet condition, respectively, thus significantly enhancing the sensing capability. Therefore, we believe the proposed FPS can increase device security owing to its excellent performance. [ABSTRACT FROM AUTHOR]

Channel-shortening effect (CSE) in oxide thin film transistors (TFTs) is a crucial issue that must be resolved for applications in ultra-high-resolution displays. One of the origins of the CSE is the diffusion of a shallow donor such as hydrogen from other layers into the channel. In this study, we investigated for the first time the CSE of self-aligned Al-doped In-Sn-Zn-O (Al-ITZO) TFTs with planar and trench structures. The TFTs with planar structures exhibited severe negative $\text{V}_{ {{ON}}}$ shifts after an annealing process, whereas the TFTs with trench structures were barely affected, thereby exhibiting excellent ON/ OFF characteristics. The vertical channel in the trench TFT had higher resistance than the horizontal channel because of a back-sidewall roughness and thin channel. The high resistance of vertical channels played a significant role in determining the ON/ OFF characteristics of Al-ITZO TFT, where $\text{V}_{ {{ON}}}$ remained constant until the diffused shallow donors made the resistive vertical channels become conductive. Based on these unique operation characteristics, the suppression of CSE in a trench TFT was demonstrated even under a high annealing temperature. Trench TFT exhibited higher mobility, higher drain currents, and higher stability than planar TFT, thus making it suitable for ultra-high-resolution displays. [ABSTRACT FROM AUTHOR]

We report how the intrinsic film stress of Mo source and drain (S/D) electrodes affects the electrical properties of Al doped InZnSnO thin-film transistors (TFTs). By controlling the Ar pressure during the sputtering process, Mo films with different film stresses (1948.2 MPa and 168.8 MPa) were formed. Two kinds of TFTs were fabricated applying these films as S/D electrodes. The TFTs made with the high-stress S/D showed linear mobility ($\mu _{\text {lin}}$) of 29.44 cm2/Vs and hysteresis of 3.39 V while the TFTs with the low-stress S/D showed $\mu _{\text {lin}}$ of 35.25 cm2 /Vs and hysteresis of 1.97 V. Under positive bias temperature stress (1 MV/cm, 60°C, 3600 s), $\text{V}_{\text {on}}$ was 4.48 V and 7.28 V for the TFTs with the low-stress S/D and high-stress S/D, respectively. X-ray photoelectron spectroscopy and finite element (FE) simulation results revealed that oxygen deficient sites in the active layer generated by the film stress of the Mo S/D induced degradation of the device characteristics. [ABSTRACT FROM AUTHOR]

Highly transparent and low-resistive multilayered gate electrodes, MoO3/indium–tin oxide (ITO)/Ag/ZnS (MIAZ) playing as the high-work-function layer, the nonreactive interface layer, the lateral conduction layer, and the index-matching layer, respectively, have been investigated for the application to the transparent oxide thin-film transistors (TFTs). The transmittance of the optimized MIAZ electrode is 92.46% and the sheet resistance is 7.77~\Omega / \Box . The top gate InGaZnO TFT with this gate electrode shows the mobility of 11.57 cm2/( \text {V}\cdot ~\text {s} ) and positive V_{\text {th}}$ of 0.210 V compared with that with single ITO gate electrode of which V_{\text {th}} is −0.086 V. [ABSTRACT FROM AUTHOR]

We fabricated amorphous AlZnSnInO TFT with back channel etch structure. Source/drain electrode of molybdenum (Mo) was formed using mixed acid based Mo/Al/Mo etchant for the first time in the fabrication of a-oxide BCE TFT. SEM and ESCA analysis showed no Mo residue on the surface of active layer. The BCE AlZnSnInO TFT showed mobility of 23.2 cm2/V.s, S.S of 0.13 V/dec., and Von of -0.5V. We show highly stable high mobility BCE TFT achieved by optimizing passivation process and active layer deposition condition. [ABSTRACT FROM AUTHOR]

We investigated effect of Cu barrier materials on the back channel etched (BCE) oxide thin film transistor (TFT). When using Cu etchant, MoAl and Mo‐Al‐Ti show better etch selectivity for Al:ITZO layer than Mo‐Ti. The BCE TFTs with Cu barrier source/drain layers show good S.S. and Von characteristics with mobility higher than 35 cm2/V.s. [ABSTRACT FROM AUTHOR]

• High mobility (30 cm2/Vs) self-aligned oxide TFTs is introduced by applying Cu diffusion barriers. (Mo, Mo‒Ti, Mo‒Al) • The origin of the channel-shortening effect was observed. • Self-aligned oxide TFTs with Mo-Al alloy show highly stable characteristics against channel-shortening effect. ga1 Developing high-resolution displays to achieve realistic images have been in a great demand recently regardless of the display size. However, in the backplane technology, the channel-shortening effect is a serious obstacle in realizing oxide thin film transistors (TFTs) with short channel lengths. In this study, we investigated the channel-shortening effect of Al-doped InSnZnO (Al:ITZO) thin-film transistors (TFTs) with Mo and Mo-based alloy Cu diffusion barriers and proposed Mo‒Al alloy as a Cu diffusion barrier to effectively reduce the channel-shortening effect. The TFTs with the Mo (Cu diffusion barrier) exhibited negative V on shifts and a channel-shortening length (ΔL) of 3.52 µm at an annealing temperature of 290 °C, although no chemical reaction occurred at the Mo/Al:ITZO interfaces. In addition, the TFTs with the Mo‒Ti (Cu diffusion barrier) showed the largest ΔV on and ΔL values at various annealing temperatures. The material and electrical analysis results confirmed that the hydrogen diffusion from the source/drain region is the main cause of the channel-shortening effect. Thus, the TFTs with the Mo‒Al (Cu diffusion barrier) exhibited excellent characteristics against the channel-shortening effect by forming a uniform and thin Al 2 O 3 layer at the Mo‒Al/Al:ITZO interface and preventing the hydrogen diffusion. The ΔV on remained almost unchanged, and the ΔL was 1.61 µm up to an annealing temperature of 290 °C. This study suggests a highly beneficial method for producing oxide TFTs, while suppressing the channel-shortening effect by tailoring the interface between source/drain and active layer using an appropriate Cu diffusion electrode. [ABSTRACT FROM AUTHOR]