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Electrocardiography (ECG) is an essential technique to assess cardiovascular conditions and monitor physical activities. While the concept is mature, issues surrounding sampling convenience and device adoption as well as maintaining signal quality under artifacts remain a problem. In this article, we present a high-performing wearable ECG armband on the upper left arm. It is equipped with miniaturized hardware, capable of data storage and wireless communication. We evaluate different electrode configurations by conducting ECG measurements both at the static state and under motion and using improved algorithms to quantify data quality and assess the agreement between the proposed new technique and the gold standard. The optimal electrode position is determined by balancing wearable suitability and signal quality. We propose an electronic textile (E-textile) armband with improved design. It offers favorable wearing comfort and a fashionable appearance without sacrificing data quality. Its contact pressure is measured to get a better picture of intimacy and clothing comfort. Our system provides real-time and noise-resilient ECG data without interrupting daily life and can be implemented in use cases that warrant continuous ECG monitoring. [ABSTRACT FROM AUTHOR]

We have investigated the effect of ultrathin Al–Ta-based capping layers on \HfO2 and experimentally demonstrated that, with proper Al and Ta composition, an AlTaO capping layer is a good candidate dielectric for PMOSFET devices. Lower threshold voltage and significantly improved mobility were observed with AlTaO capping without degrading the dielectric properties. The addition of Ta in an AlTaO structure produces d-states in the \Al2\O3 matrix, resulting in an additional VT shift toward the PMOS band edge. This AlTaO capping layer not only modulates the device VT suitably for PMOS applications but also retards Al diffusion through the \HfO2 layer, preventing Al-caused mobility degradation. Furthermore, the incorporation of a capping layer can improve reliability characteristics during the negative bias stress. [ABSTRACT FROM PUBLISHER]

This letter presents a methodology to accurately extract the work function of metal electrodes on high-κ dielectrics with various charge distributions. A mathematical analysis including sources of errors were used to study the effect of charge distribution in gate dielectric stacks on the flatband voltage of the device. The calculations are verified by experimental results obtained for Ru-Ta alloys on HfO2 and SiO2 gate dielectric stacks. It is shown that accounting for the appropriate charge model is imperative for accurate calculation of workfunction on high-κ/SiO2 gate dielectric stacks. [ABSTRACT FROM AUTHOR]

This letter investigates the work function tuning of nickel/gadolinium (Ni/Gd) fully silicided (FUSI) gate electrodes on HfSiOx dielectrics. It was found that as the percentage of Gd in the Ni/Gd increased from 10% to 30%, the effective work function value after a one-step 450-° C FUSI anneal decreased from 4.75 to 4.35 eV. In addition, the presence of Gd also resulted in lowering of equivalent oxide thickness (EOT) values. The mechanism for a decreased EOT is attributed to the reduction of low-κ interfacial layers by the presence of Gd in the gate stack. The decrease in work function is attributed to the creation of oxygen vacancies within the high-κ layer created by the presence of Gd layer. [ABSTRACT FROM AUTHOR]

This letter evaluates Ru and W capping layers for MoTa metal gate electrodes in MOS capacitor applications. The authors report that the oxygen diffusion from the capping layer plays an important role in determining the MoTa alloy effective work function value on SiO2. A MoTa alloy metal gate with Ru capping exhibits stable effective work function up to 900 °C annealing but is not stable with W capping. Auger electron spectroscopy and Rutherford backscattering spectroscopy analyses show minimal oxygen diffusion into MoTa gate stacks with Ru capping while severe oxygen diffusion into the gate is observed with W capping metal after 900 °C annealing. Current-voltage analysis also demonstrates different barrier heights of MoTa on SiO2 with Ru or W capping layer after 900 °C annealing, confirming the effective work function value change. [ABSTRACT FROM AUTHOR]

Lateral conductivity within a monolayer is a key factor in the implementation of emerging dense molecular memory devices since it determines the degree of cross talk between cells. Lateral interactions within a monolayer could also lead to loss of charge through defective sites. Existing characterization techniques are limited to probing the electrical communication between molecules and attached electrodes. In this paper we demonstrate a test structure consisting of n type and p type doped silicon islands to isolate vertical conduction from lateral conduction. This structure is a useful characterization tool for tailoring the intrinsic properties of the molecules for information storage. [ABSTRACT FROM AUTHOR]

Metal gate electrodes consisting of three layered stacks of metals are investigated for complementary metal-oxide-semiconductor device applications. It was observed that the effective work function of the entire gate electrode stack was dominated by the work function of the first metal layer (50 Å of tantalum nitride) contacting the gate dielectric. No significant difference in the effective oxide thickness was observed in devices with and without the initial tantalum nitride layer. The potential reasons for this, based on the penetration of an electron wave function from the gate electrode to the gate dielectric and gate depletion due to longer Debye length of electrons in tantalum nitride, will be discussed. [ABSTRACT FROM AUTHOR]

Tensile-strained Si epitaxial layers (7.5 nm–17 nm) were grown on relaxed Si0.5Ge0.5 virtual substrates by ultrahigh-vacuum rapid thermal chemical vapor deposition. Metal-oxide-silicon capacitors were fabricated with SiO2 or HfO2 as gate dielectrics and Ru–Ta alloy or TaN as the metal gate electrodes. The results indicate that the interface trap density (Dit) increased as the strained silicon thickness decreased, which was attributed to the presence of Ge in the strained Si layer. Higher Dit was observed with SiO2 which may be due to Si consumption during oxidation, leading to a higher density of Ge at the interface. Leakage current density (Jg) was also observed to increase with increasing strained silicon thickness. This trend of increasing Dit and Jg with decreasing strained silicon thickness did not change after rapid thermal annealing. Both Ru–Ta and TaN gate electrodes were found to exhibit as good a performance on strained Si as on bulk Si. [ABSTRACT FROM AUTHOR]

This letter describes RuxYy as a potential candidate for dual metal complementary metal–oxide–semiconductor applications. The characterization of RuY alloys indicate that the effective work function can be controlled from 3.9 to 5.0 eV as the yttrium composition in the RuxYy is decreased in film for both PMOS and NMOS application. From x-ray photoelectron spectroscopy analysis, it was found that the Ru 3d peaks do not change as the Y composition is changed, indicating the Ru–Y bonding is very weak or undetectable in RuxYy film. However, it was also found that Y reacts with the underlying SiO2 to form yttrium silicate. In addition, in situ x-ray diffraction results did not detect the presence of Ru–Y compound in the RuxYy films. Capacitance–voltage (C–V) characterization indicated that the oxide thickness decreased as the Y composition increased. We extracted the effective barrier height of RuxYy at the metal–oxide interface via Fowler–Nordheim current analysis. The barrier height decreases as the Y composition increased. This agrees with the change of RuxYy work function which was extracted from the C–V analysis. [ABSTRACT FROM AUTHOR]

In this letter, the effect of silicon and nitrogen on the electrical properties of TaSi[sub x]N[sub y] gate electrode were investigated. The TaSi[sub x]N[sub x] films were deposited on SiO[sub 2] using reactive cosputtering of Ta and Si target in Ar and N[sub 2] ambient. The thermal stability of TaSi[sub x]N[sub y]/SiO[sub 2]/p-type Si stacks was evaluated by measuring the flatband voltage and equivalent oxide thickness at 400 °C and 900 °C in Ar. It was found that under high temperature anneals, Si-rich TaSi[sub x]N[sub y] films increased and this was attributed to the formation of a reaction layer at the electrode-dielectric interface. Reducing the Si content alone did not prevent the formation of this reaction layer while removing Si completely by utilizing TaN resulted in work functions that were too high. The presence of both Si and N was deemed necessary and their content was critical in obtaining optimized TaSi[sub x]N[sub y] gates that are suitable for NMOS devices. [ABSTRACT FROM AUTHOR]

Metal-oxide-semiconductor capacitors were used to study the interaction of Hf and Zr gate electrodes on SiO[sub 2], ZrSi[sub x]O[sub y], and ZrO[sub 2]. A large reduction in the SiO[sub 2] equivalent oxide thickness accompanied by an increase in the leakage current was observed with Hf and Zr electrodes when subjected to anneal temperatures as low as 400 °C. The reduction in electrical thickness as observed from the capacitance-voltage measurements was attributed to the combination of (a) physical thinning of the SiO[sub 2] and (b) formation of a high-K layer. A severe instability of Zr and Hf electrodes was also observed on ZrSi[sub x]O[sub y] and ZrO[sub 2] dielectrics. This behavior of Zr and Hf gates was attributed to high negative enthalpy of oxide formation and high oxygen solubility resulting in the reduction of the gate dielectric and subsequent oxygen diffusion to the gate electrode. © 2001 American Institute of Physics. [ABSTRACT FROM AUTHOR]

The rutile stoichiometric phase of RuO[sub 2], deposited via reactive sputtering, was evaluated as a gate electrode on chemical vapor deposited ZrO[sub 2] and Zr silicate for Si-p-type metal-oxide-semiconductor (PMOS) devices. Thermal and chemical stability of the electrodes was studied at annealing temperatures of 400, 600, and 800 °C in N[sub 2]. X-ray diffraction was measured to study grain structure and interface reactions. The resistivity of RuO[sub 2] films was 65.0 μΩ cm after 800 °C annealing. Electrical properties were evaluated on MOS capacitors, which indicated that the work function of RuO[sub 2] was ∼5.1 eV, compatible with PMOS devices. Post-RuO[sub 2] gate annealing up to 800 °C, resulted in only a 1.4 Å equivalent oxide thickness (T[sub ox-eq]) change and 0.2 V flatband voltage change for Zr silicate and a 4 Å T[sub ox-eq] change for ZrO[sub 2] dielectrics. Tantalum electrodes were also studied on ZrO[sub 2] as a comparison of the stability of RuO[sub 2] electrodes. © 2001 American Institute of Physics. [ABSTRACT FROM AUTHOR]