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We use a popular organic-inorganic hybrid perovskite, methyl-ammonium lead iodide (MAPbI3), for thin-film transistors (TFTs). Given the sensitivity of organic-based perovskites to wet processes, we employed an inverted coplanar TFT structure with a UV-treated, high- ${k}$ $\text{AlO}_{\textit {x}}$ gate insulator and deposited the perovskite from solution into a photoresist bank as the final process step. We also explored the impact of substitutional doping of the MAPbI3 with a smaller inorganic cation, cesium (Cs+), or the larger organic cation, formamidinium (FA), to form the mixed-A cation perovskites, $\text{FA}_{\textit {x}}$ MA1-xPbI3 and CsxMA1-xPbI3, respectively. We demonstrated a significant improvement in the TFT switching speed and ON/ OFF ratio with CsxMA1-xPbI3 but failed to achieve any transistor operation with FAxMA1-xPbI3. Incorporation of Cs into MAPbI3 reduced bulk and interfacial trap states and improved film density and morphology, whereas incorporation of FA resulted in increased surface roughness and thicker grain boundaries. [ABSTRACT FROM AUTHOR]

Short-channel Corbino thin-film transistors (TFTs) exhibit infinite output resistance beyond pinchoff when the outer-ring electrode is biased as the drain but suffer from low drain currents. It is shown here that the employment of a thin (<25 nm) amorphous oxide semiconductor and a double-gate (DG) structure (with a top-gate electrically tied to a bottom-gate) increases the drain currents of the Corbino TFTs biased in the outer-drain condition by over two times through bulk-accumulation (BA), without compromising their infinite output resistance beyond pinchoff or bias, temperate, and light stability. By experiment and through 3-D TCAD simulations, evidence of BA under DG modulation and the origin of the infinite output resistance beyond pinchoff in Corbino TFTs are also revealed in this letter. [ABSTRACT FROM PUBLISHER]

We report high-performance homojunction amorphous-indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs) with low-resistive a-IGZO source/drain (S/D) electrodes. The a-IGZO S/D electrodes are selectively treated with high-power NF3 plasma, which reduces their resistivity from \sim 16 to 5.5 \times 10^{\vphantom {R^{R^{}}}{-3}}~\Omega \,\cdot \, cm. X-ray photoelectron spectroscopy indicates an increase in weakly bonded oxygen and a substantial amount of indium–fluorine and zinc–fluorine bonds at the a-IGZO top surface (extending to \sim 7$ nm into the bulk) after plasma treatment. Temperature-dependent conductivity measurements show metallic behavior of the a-IGZO after treatment. It is concluded that fluorine atoms substitute for oxygen atoms—generating free electrons in the process and/or occupy oxygen vacancy sites—eliminating electron trap sites. As a result, the homojunction TFTs show good ON-state characteristics with typical field-effect mobility, subthreshold gate-voltage swing, and turn-ON voltage of 19 ± 1 cm ^{2} / \text{V}\,\cdot \,\text{s} , 178 ± 30 mV/decade, and −3.2 ± 1.5 V, respectively. Good stability at high temperature and under bias and light stress are also exhibited by the homojunction TFTs, verifying a stable doping effect by the NF3 plasma treatment. [ABSTRACT FROM PUBLISHER]

A high-gain source follower, utilizing oxide TFTs with a Corbino (circular) structure, is reported. Given the infinite output resistance exhibited by Corbino TFTs in the outer-drain condition (i.e., when the outer electrode is biased as the drain), the Corbino TFT-based source follower provides higher gain in operation than its rectangular TFT-based counterparts. [ABSTRACT FROM AUTHOR]

We report a low-voltage-driven amorphous indium–gallium–zinc oxide (a-IGZO) semiconductor-based Corbino (circular) thin-film transistor (TFT) with infinite output resistance beyond pinchoff. The Corbino TFT has inner and outer concentric ring electrodes, and when the latter is the drain, channel width (W) decreases with channel length (L), such that the W/L ratio is not changed after pinchoff. As demonstrated herein, this a-IGZO Corbino TFT is, therefore, a good candidate for uniform current drivers in applications, such as active-matrix organic light-emitting diode display pixels, where it would maintain the same drive (diode) currents, even with variations in supply voltage ( \(V_{\mathrm {{DD}}}\) ). [ABSTRACT FROM PUBLISHER]

Intrinsic mobility and intrinsic channel resistance (RCH) of amorphous, In–Ga–Zn–O (a-IGZO) thin-film transistors (TFTs) with varying channel length (L) are investigated using a gated four-probe back-channel-etched TFT design. The intrinsic R_{\rm CH} is found to decrease from {\sim}{500} to \sim250~k\Omega per unit area by increasing VGS from 10 to 20 V. The intrinsic mobility is \sim17~cm^2/V\cdots , which is about 20% higher than that derived from the normal two-point probe measurements. Source and drain parasitic resistance (RPAR) of the a-IGZO TFTs is found to be of the same order of magnitude as the RCH —which is different from hydrogenated amorphous-silicon (a-Si:H) TFTs, where TFT operation is dominated by RPAR . [ABSTRACT FROM AUTHOR]

We demonstrated the high performance back-channel-etched (BCE) amorphous-InGaZnO (a-IGZO) thin-film transistor (TFT) circuits. The TFTs exhibited the field-effect mobility, turn-on voltage and subthreshold swing of 18 cm2/V•s, -0.1 V, and 258 mV/dec, respectively. The oscillation frequency of an 11 stages ring-oscillator is ~334.1 kHz, at VDD = 20 V. The 320 stages 11T2C shift-register operated well up to the last stage with rising and falling times of 950 and 690 ns, respectively. Good performance is attributed to damage-free back channel wet etch process and small overlap capacitance between the gate and source/drain electrodes. [ABSTRACT FROM AUTHOR]

A dual-gate thin-film transistor (TFT) has two gate electrodes. In inverted, staggered TFTs, the primary gate is usually the bottom gate (BG) and the TFT's threshold voltage (VTH) can be adjusted by applying a constant bias to the secondary gate, the top gate (TG), while scanning the BG. Dual-gate TFTs are being used as the load TFT in oxide semiconductor-based inverters, where the TG is biased positively to shift the VTH negatively and, thereby improving the inverter's output swing. Here, we show that the same can be achieved by the use of a floating TG. Furthermore, we show that the noise margin of the inverter can also be controlled by adding a biased TG to the driving TFT. [ABSTRACT FROM PUBLISHER]

The overlap between gate and source/drain electrodes gives rise to parasitic capacitance ( C\text {gd} /), which causes RC signal delay in thin-film transistor (TFT) circuits. Here, we show that in amorphous-indium–gallium–zinc-oxide TFTs, offsets as large as 0.5~\mu \textm , result in only slight reductions in drain-current, such that (compared with single-gate TFTs with 2.5- \mu \textm gate-to-source/drain overlaps) an overall three times increase in switching speed can be achieved in dual-gate TFTs with offset top-gates shorted to offset bottom-gates. The high switching speed ( $\sim 18$ ns/stage delay), which is a combined effect of the bulk-accumulation achieved by shorting the two gates and zero C\text {gd} , results in high-speed amorphous oxide TFT-based circuits. [ABSTRACT FROM AUTHOR]

The effect of bulk accumulation on switching speed of dual-gate amorphous indium–gallium–zinc-oxide thin-film transistor (TFT)-based circuits is investigated. Given that bulk accumulation is achieved by synchronized driving of the top gate (TG) and bottom gate, it can be modulated by varying the length of the TG ( \textrm L{{\textrm {TG}}} ) for fixed source–drain distance ( $L$ ). It is confirmed from fabricated ring oscillators that switching speed increases with increasing \textrm L{{\textrm {TG}}} for fixed $L$ , verifying that bulk accumulation improves switching speed. However, switching speed drops dramatically when the TG overlaps the source/drain electrodes due to additional parasitic capacitance. TFT-circuits with the longest, but nonoverlapping TGs are demonstrated to exhibit the fastest switching speed; operation frequency exceeding 2.63 MHz for input voltage \textrm {V}_{{{\textrm {DD}}}} of 20 V, which is also the fastest among all inverted staggered amorphous-oxide-semiconductor TFT-based circuits. [ABSTRACT FROM AUTHOR]

A highly stable, dual-gate (DG) amorphous, indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) with an offset top-gate (TG) is reported. Given that both gates are opaque and electrically tied together, the TG functions as a light-shield and drain-current (I \({}_{\mathrm {DS}}\) ) enhancer as synchronized gate-voltage (V \({}_{\mathrm {GS}}\) ) sweep induces bulk-accumulation (BA) at positive voltages. It is demonstrated here that regardless of the offsets between the TG and source/drain electrode, this BA a-IGZO TFT is immune to negative bias and light-illumination stress (NBIS) when the TG covers at least 50% of the channel region. Therefore, high performance BA a-IGZO TFTs that are also immune to NBIS can be designed without introducing additional parasitic capacitance that occurs when the TG overlaps the source and/or drain electrode(s). [ABSTRACT FROM AUTHOR]

A high-performance inverter implemented with single-gated driving and dual-gated load amorphous-indium–gallium–zinc–oxide thin-film transistors (TFTs) is demonstrated. The threshold voltage of the load TFT shifts to the negative gate voltage direction when a constant positive bias is applied on the top gate while sweeping the bottom gate. Using a positive top gate bias, the load TFT can be operated in the depletion mode to realize inverters with excellent switching characteristics, such as a wider swing range and a higher noise margin. [ABSTRACT FROM AUTHOR]