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In this article, a novel reverse-conducting lateral insulated gate bipolar transistor (RC-LIGBT) with embedded diode and p-type Schottky Barrier Diode (p-SBD) is proposed. The two diodes are connected in series through a floating electrode, which provides a current path for carriers in reverse-conducting mode. Compared with the Separated Shorted-Anode RCLIGBT (SSA-RC-LIGBT), the proposed structure not only eliminates the snapback voltage (Δ VSB) but also avoids the waste of device area. Therefore, the superior reverse recovery characteristics and excellent tradeoff relationship between ON-state voltage (VON) and turn-off loss (EOFF) are obtained. The reverse recovery charge of the proposed RC-LIGBT shows 43.9% and 63.2% reduction compared with those of the SSA-RC-LIGBT with LB (distance between the p+ collector and the shorted n+ collector) being 34 and 64μm, respectively. The turn-off loss of the proposed RC-LIGBT at VON = 2.6 V is reduced by 68.2% and 87.1% compared with those of the SSA-RC-LIGBT with Δ VSB = 0.48 V and Δ VSB = 0.17 V, respectively. Moreover, the proposed RC-LIGBT has a self-adjusted collector injection efficiency under different temperatures to dramatically improve the Short Circuit Safe Operation Area (SCSOA). [ABSTRACT FROM AUTHOR]

In this paper, a super-junction p-type lateral diffused metal–oxide–semiconductor transistor (SJ-pLDMOS) utilizing electron to enhance the current capability is proposed. The proposed SJ-pLDMOS has an n-channel in the drain region and is controlled by an auto-generated voltage signal (${V}_{\mathrm {\textsf {Gn}}}$). The voltage signal ${V}_{\mathrm {\textsf {Gn}}}$ is generated during the ON- and OFF-state of the hole current which flows across an integrated resistor (${R}\text{p}$) implemented in the p-base region. Thus, the proposed SJ-pLDMOS utilizes both hole and electron currents to significantly enhance the current capability. Simulation results show that the current capability of the proposed SJ-pLDMOS without any conductivity modulation effect is comparable with that of a super-junction nLDMOS (SJ-nLDMOS). The total power loss of the proposed super-junction pLDMOS (SJ-pLDMOS) is reduced by about 26.7% and 18% compared with that of the SJ-nLDMOS and Triple Resurf nLDMOS (TR nLDMOS) at a rated load current density of $25~\mu \text{A}/\mu \text{m}$ , respectively. [ABSTRACT FROM AUTHOR]

In this letter, a p-channel lateral double-diffused MOSFET (p-LDMOS) with double electron paths used to enhance the current capability is proposed. The proposed p-LDMOS has two n-channels that are controlled by an auto-generated voltage signal (${V}_{\text {Gn}}$). The voltage signal ${V}_{\text {Gn}}$ is generated during the ON and OFF states of the hole current that flows across an integrated resistor ($R_{\text {p}}$) implemented in the P-base region. Thus, the current capability of the p-LDMOS can be significantly enhanced by the introduced electron current. The simulation results show that the current capability of the proposed p-LDMOS can be comparable to that of the n-type triple RESURF technique without any conductivity modulation effect. The power loss of the proposed p-LDMOS is reduced by approximately 78.6% and 15.6% compared with the triple RESURF p-LDMOS and n-LDMOS, respectively, at a rated load current density of $25~\mu \text{A}/\mu \text{m}$. [ABSTRACT FROM AUTHOR]

A new type of “quasi-p-lateral diffused metal oxide semiconductor” (quasi-p-LDMOS), in which electrons are used as conductive carriers in the drift region is proposed. A floating electrode F is used in the “quasi-p-LDMOS” to transform the hole current into electron current. Then, by using an integrated low-voltage power and an inverter to control the electron current automatically, the specific on-resistance (R on,sp) is significantly reduced and the device can be successfully turned on and off. Simulation results show that the Ron,sp is 12.77 and 31 mΩ·cm2 for a 349 and 630 V “quasi-p-LDMOS,” being only about 19.7% and 14.7% of a Triple-RESURF p-LDMOS, respectively. Moreover, the Ron,sp is even lower than that of a Triple-RESURF n-LDMOS at the same rated breakdown voltage. The figure of merit of the device is 3 to 7 times of that of state-of-the-arts. The “quasi-p-LDMOS” is designed as a low-side device in a new high-voltage CMOS circuit. By applying the “quasi-p-LDMOS” in the CMOS circuit, the total power loss is much lower than that of a conventional half-bridge circuit in a wide operating frequency. The “quasi-p-LDMOS” is suitable for smart power integrated circuit to improve both the integration level and system efficiency, and simplifies the circuit design. [ABSTRACT FROM PUBLISHER]

The structure of multilevel low-voltage power supplies with a self-clamped characteristic is proposed and experimentally demonstrated using a 0.5- \mu \textm BiCMOS process. The power supply can achieve two output voltages by its intrinsically integrated structure with the values of 25.0 and 13.6 V when the applied high voltage is 90 V and the two load resistances are both 30 \textk\Omega . The two output voltages also appear good stability. When the applied high voltage is changed from 90 to 150 V, its line regulation is 0.07%/V, and when the two load resistances vary within 30–100 \textk\Omega , its load regulation is 9.6%. The proposed power supply is able to be integrated with most high-voltage devices without passive components and additional processes, which makes it considerable in the applications of high-voltage integrated circuits. [ABSTRACT FROM PUBLISHER]