Search

Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real-time portable domain. Operating the Si-MOSFET in subthreshold regions degrades the circuit performance in terms of speed and also increases the well-designed circuit parameter spreading due to process, voltage, and temperature variations. This may cause the subthreshold circuit failure at very low supply voltage. It is essential to examine the robustness of most emerging devices against PVT variations. Therefore, this paper investigates and compares the performance of most promising upcoming devices like CNFET and DG FinFET in subthreshold regions. Effect of PVT variation on performance of CNFET and DG FinFET has been explored and it is found that CNFET is more robust than DG-FinFET under subthreshold conditions against PVT variations.

Bulk CMOS technology is facing enormous challenges at channel lengths below 45 nm such as gate tunneling, device mismatch, random dopant fluctuations, mobility degradation, etc. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology for its rapid commercialization. Therefore, this paper presents a comparative study of CMOS version and CNFET version of Operational amplifier at 32-nm technology nodes. The performance of CNFET based amplifier has been thoroughly investigated in terms of its input resistance, output resistance and AC gain. This study shows that there is considerable improvement in the above feature of amplifier using CNFET. It is founded that CNFET based amplifier have 9 times AC gain, 100 times input resistance and output resistance decrease by 9 times compared to MOSFET based amplifier at 32-nm technology node. Furthermore, comparison between two technologies for same gain bandwidth product (GBP) has also been presented.

The paper presents the performance comparison of a wide bandwidth Dual-X Current Conveyor, designed using CMOS and Hybrid approaches at 32nm technology node. A hybrid configuration is obtained by utilizing both CMOS and CNFET on the same chip. CNFETs seems to be a good prospect for extending the saturating Moore's Law because of it's higher mobility, scalability and better channel electrostatics. 3-dB current bandwidth, port-resistances along with power consumption have been chosen as the key parameters for comparison. The work in this paper shows that through properly designed hybrid configuration, an edge in performance could be obtained over Si CMOS, thus making it a good proposition for ultra wideband circuits and systems.

This paper presents a study of MTJ-based logic circuit in terms of propagation delay, power dissipation, and power-delay product. The paper also analyzes impact of PVT process, voltage, and temperature) variations on most of the design metrics of logic circuit and compares the results with hose conventional CMOS logic circuit. The MTJ-based logic circuit are found to be robust compared with conventional CMOS logic circuits at the cost longer delay and higher power dissipation.

Ultra low power -- efficient VLSI circuits design received wide attention due to rapid growth of portable applications. The portable domain places inflexible constraint on the power consumption. Though, device operating in sub threshold region shows huge potential towards satisfying the ULP requirement, it holds lots of difficult design issues. As integration density of interconnects increases at every technology node, increased delay and cross talk effects may becomes a more challenging design problem particularly for sub threshold interconnects. Nanometer sub threshold global interconnect faces sub threshold driver design challenges and problems due to increased interconnect capacitance. This paper examined and compared the effect of cross talk on delay for mixed wall carbon nano tube and Cu interconnects. This work reports new aspect ratio for global interconnect to reduce the effect of cross talk on interconnect performance under sub threshold conditions.