Search

In this paper, an implementation of a simulated grounded inductor (SGI) based on a recently developed active building block called second-generation voltage conveyor (VCII) is proposed. The proposed SGI employs two VCIIs, two resistors, and one grounded capacitor, which is preferred when integration is involved. More importantly, unlike most of the other previously reported SGIs, this one is free from any restrictive matching conditions. A complete analysis of nonidealities along with sensitivity treatment by considering parasitic impedances and nonideal gains of the VCII are performed. A simple VCII circuit is designed to be used in the implementation of the proposed SGI. To support the presented theory, Pspice simulation results using 0.18-µm CMOS technology parameters and supply voltage of ±0.9 V are provided. On the basis of the achieved results, the proposed SGI operates in a good agreement with an ideal inductor. The power consumption is only 0.65 mW, and the parasitic series impedance is approximately 191.9 ?. The applicability of the proposed SGI is tested by using it in a standard second-order high-pass RLC filter. © 2020 John Wiley & Sons, Ltd.

Silicon Photomultipliers can be considered as novel detectors with single-photon counting capability. In this work, we present an integrable CMOS interface, based on second-generation Rail-To-Rail voltage conveyor (VCII-RTR), for Silicon-based photomultiplier. The VCII-RTR works as a transimpedance amplifier guaranteeing a constant bandwidth with respect to the wanted tunable gain. We here propose only simulation results which show general good circuit performances, confirming that the proposed architecture can be used in Si-based Silicon Photomultiplier. The already proposed and here utilized VCII-RTR has a total power consumption of 120 μW with a voltage swing on the Z terminal of ±0.83 V, while on the X terminals it is ±0.72 V.

In this paper we propose a new versatile full wave rectifier circuit using voltage conveyor (VCs) as active blocks. The proposed circuit uses two VCs, a single grounded resistor and two diodes. Compared to other previously reported rectifier circuits, it shows a simple and compact structure, employing the minimum possible number of elements. Moreover, the rectified output is available in forms of both voltage and current signals, at low impedance voltage output Z port and high impedance X port of VC, respectively. Therefore, for practical use, the proposed rectifier is cascadable without the need for extra voltage and current buffers. In addition, also the input signal can be applied in both forms of a current and of a voltage. To validate the presented theory, SPICE simulations, using 0.35 µm CMOS technology parameters and supply voltage of ±1.65 V, are reported, together with a set of measurements conducted over an equivalent discrete-level circuit, where AD844s were used to mimic VCs behavior.

In this paper, a new current-mode instrumentation amplifier with electronic tuning and low-voltage operation capabilities is presented. Simplicity is other important feature so that the whole circuit is composed of only 20 transistors. All the above have been achieved using MOS transistors biased in the sub-threshold region. The required current-controlled gain stage has been implemented using an appropriate translinear loop which is fed by the output of a current subtraction stage, realized through the employment of flipped voltage follower based current-mirrors. The performance of the presented amplifier is evaluated through simulation results, using the Cadence suite and MOS transistors models provided by the Austria Mikro Systeme 0.35 μ m CMOS process. The differential gain was 20 – 40 dB , the Common-Mode Rejection Ratio (CMRR) was 44.4 – 48.9 dB , achieved at power dissipation 72.75 – 386.1 nW . The bandwidth was 7 kHz and the Total Harmonic Distortion (THD) was 2 % for an input signal with amplitude equal to 550 pA. As an application example, the proposed current-mode instrumentation amplifier has been employed for removing the noise component in electrocardiogram signals.

A new plus-type second-generation voltage conveyor (VCII+) based first-order mixed-mode (MM) all-pass (AP) filter is proposed in this study. The proposed MM AP filter employs two VCII+s, three resistors and one grounded capacitor. It has low input and high output impedances for the current-mode selection while it has low input and low output impedances for the transimpedance-mode selection. The AP filter gain is unity for the current output while it is adjustable for the voltage output via a grounded resistor. However, a single passive component matching condition is needed for the proposed MM AP filter. Complete non-ideal analysis by taking into account all the parasitic resistors and non-ideal gains of the VCII+ is performed. The presented theory is verified through SPICE simulations by using supply voltage of ± 0.9 V and 0.18 µm Taiwan Semiconductor Manufacturing Company complementary metal oxide semiconductor technology parameters. © The Institution of Engineering and Technology 2020

In this paper two new first order filter topologies realizing low-pass/all-pass (LP/AP) and low-pass/high-pass (LP/HP) outputs using electronically controllable second generation voltage conveyors (CVCIIs) are presented. Unlike second generation voltage conveyors (VCII), in CVCII each performance parameter, including ports, parasitic impedances, current and/or voltage gains can be electronically varied. Here, in particular, the proposed filter topologies are based on two CVCIIs, one resistor and one capacitor. In the first topology VLP/IAP/VAP and in the second topology ILP/VLP/IHP/VHP outputs are achievable, respectively. However, the current and voltage outputs are not achievable simultaneously and a floating capacitor is used. A control current (Icon) is used to change the first CVCII Y port impedance, which sets the filter −3 dB frequency (F0) of all the outputs. Moreover, in the second topology, the gains of HP and AP outputs are electronically adjusted by means of a control voltage (Vcon). Favorably, no restricting matching condition is necessary. PSpice simulations using 0.18 µm CMOS technology and supply voltages of ±0.9V show that by changing Icon from 0.5 µA to 50 µA, F0 is varied from 89 kHz to 1 MHz. Similarly, for a Vcon variation from −0.9 V to 0.185 V, the gains of IAP and IHP vary from 30 dB to 0 dB and those of VAP and VHP vary from 100 dB to 20 dB. The total harmonic distortion (THD) is about 8%. The power consumption is from 0.385 mW to 1.057 mW.

In this chapter, Current-Mode Instrumentation Amplifiers (CMIAs) with the capability of having an electronically controllable gain are discussed. These CMIAs do not require variable passive resistors to change gain but the latter is adjusted by means of a control voltage or current. This kind of instrumentation amplifiers is more suitable for IC realization. We divide electronically controllable CMIAs into two categories. In the first category, gain is varied by means of either bias current or bias voltage of the used active building blocks. Here, electronic controllability is achieved at the expense of higher power consumption. In the second category, gain is varied by means of an electronically variable active resistor. Therefore, they have much simpler design and show less power consumption. © 2019, Springer Nature Switzerland AG.

In vast majority of operational amplifiers, output transistor current is not independently accessible. Op-Amp power supply current sensing is a simple technique for detecting output transistor current from the Op-Amp power supply leads. This technique was first introduced in 1979 to implement voltage controlled current sources and current controlled current sources [1]. It has been implemented by connecting current mirrors to Op-Amp supply leads and makes possible to gain access to output transistor current separately. © 2019, Springer Nature Switzerland AG.

Current chapter deals with Wheatstone Bridges with the focus on Current-Mode Wheatstone Bridge and its associated signal conditioning circuits. The operation, advantages and drawbacks of each circuit are discussed in detail. To make the comparison between traditional Voltage-Mode Wheatstone Bridge and Current-Mode Wheatstone Bridge more convenient, at the beginning of this chapter, the concept of Voltage-Mode Wheatstone Bridge is briefly summarized. The theory of Mixed-Mode Wheatstone Bridge and read-out circuits are also included. © 2019, Springer Nature Switzerland AG.

In this paper a high-performance low-voltage low-power CMOS second-generation current conveyor (CCII) is presented. The proposed CCII is based on super transistor (ST) and enables low input impedance at X terminal and high output impedance at Z terminal. It also utilizes a novel power saving strategy in which a single NMOS cascode current mirror conveys X terminal current to Z terminal, provides high impedance at Z terminal and reduces the X terminal impedance all together resulting in a low-power and compact structure. As another advantage, only NMOS transistors are used in processing voltage and current signals granting the proposed CCII high frequency operation. PMOS transistors are used only for biasing. However, the proposed CCII cannot provide infinite impedance at Y terminal. HSPICE simulations using 0.18 µm parameters and supply voltage of ±0.9 V confirms that the proposed CCII exhibits impedances of 0.155 Ω, 1.6 MΩ and 47 kΩ at X, Z and Y terminals, respectively. Voltage and current bandwidths are also 377 MHz and 159 MHz, respectively. Some of the applications of the proposed CCII are given. DOI: http://dx.doi.org/10.5755/j01.eie.24.2.17948

This brief presents a comprehensive study on a particular kind of conveyor called second-generation voltage conveyor (VCII). This building block is based on voltage conveying concept and is the dual of second generation current conveyor (CCII). It is shown that VCII is a very useful block in those configurations where CCII is limited, in terms of number of active blocks. The results of this brief are helpful in choosing the best building block between CCII and VCII for each specific application. Finally, for the first time, the CMOS implementation of VCII is also presented. Simulation results with PSPICE using 0.35- ${\mu }\text{m}$ CMOS technology and supply voltage of ±1.65 V are given to approve the theory.

Minaei, Shahram (Dogus Author) In this paper a new topology for implementing Current-Mode Instrumentation Amplifiers (CMIA) is presented. The proposed CMIA is based on two single input-multiple output (SI-MO) current operational amplifiers (COAs) as basic building blocks and 2 resistors. To electronically control the differential mode gain, a transistor operating in triode region is used which acts as a variable resistor. The significant feature of the proposed CMIA is that the active building blocks operate in closed loop configuration. Therefore it exhibits numerous remarkable features such as improved frequency performance, low THD and very low input impedance. In addition, it has fully differential output which reduces the output noise and increases its application. The proposed CMIA is analyzed and simulated with SPICE program using parameters of 0.18 mu m CMOS technology and supply voltage of +/- 0.9 V.

In this paper, a novel low voltage low power CMOS second generation voltage conveyor (VCII) with an improved voltage range at both the X and Z terminals is presented. The proposed VCII is formed by a current buffer based on a class AB regulated common-gate stage and a modified rail-to-rail voltage buffer. Spice simulation results using LFoundry 0.15&nbsp, &mu, m low-Vth CMOS technology with a &plusmn, 0.9&nbsp, V supply voltage are provided to demonstrate the validity of the designed circuit. Thanks to the class AB behavior, from a bias current of 10&nbsp, &micro, A, the proposed VCII is capable of driving 0.5&nbsp, mA on the X terminal, with a total power consumption of 120 &micro, W. The allowed voltage swing on the Z terminal is at least equal to &plusmn, 0.83&nbsp, V, while on the X terminals it is &plusmn, 0.72&nbsp, V. Both DC and AC voltage and current gains are provided, and time domain simulations, where the voltage conveyor is used as a transimpedance amplifier (TIA), are also presented. A final table that summarizes the main features of the circuit, comparing them with the literature, is also given.

This paper is assigned to the design of voltage feedback current amplifiers (VFCAs). Their operation and interesting characteristics are covered and a novel CMOS VFCA is presented. New ideas based on super transistors (STs) are devised and used to design a high performance VFCA. Benefiting from the interesting properties of STs, the proposed VFCA exhibits high linearity, high output impedance, very low input impedance and wide bandwidth. The proposed circuit is designed using TSMC 0.18 μm CMOS technology parameters and supply voltage of ±0.75 V. Simulation results with HSPICE show low THD of −60 dB at the output signal, very low impedance of 0.6 Ω and 0.2 Ω at the input and feedback ports respectively and high output impedance of 10 MΩ. Moreover it can provide wide −3 dB bandwidth of 15.5 MHz. The results prove the high capability of the VFCA in current mode signal processing and encourage strong motivation to develop commercially available VFCAs.

Minaei, Shahram (Dogus Author) -- Conference full title: 2017 European Conference on Circuit Theory and Design (ECCTD); Catania; Italy; 4-6 September 2017. In this paper, a new electronically controllable current-mode instrumentation amplifier (CMIA) is presented. The proposed CMIA is based on only two electronically tunable second-generation current conveyors (ECCIIs). It does not need any passive element which makes it highly suitable for integration. More interestingly, high CMRR is achieved without the need for matching between active elements. Its input and output signals are current and it enjoys low input and high output impedances, respectively. Due to the inefficiency of the existing ECCIIs, a new ECCII circuit is also designed to be used in the proposed CMIA structure. PSPICE simulation results using 0.18μm TSMC CMOS technology and supply voltage of ±0.9V, shows CMRR of 42dB and fixed -3dB bandwidth of 68MHz for differential-mode gain ranging from 0dB to 27dB.

In this paper, a novel topology for implementing resistor-free current-mode instrumentation amplifier (CMIA) is presented. Unlike the other previously reported instrumentation amplifiers (IAs), in which input and/or output signals are in voltage domain, the input and output signals in the proposed structure are current signals and signal processing is also completely done in current domain benefiting from the full advantages of current-mode signal processing. Interestingly the CMRR of the proposed topology is wholly determined by only five transistors. Compared to the most of the previously reported IAs in which at least two active elements are used to attain high common-mode rejection ratio (CMRR) resulting in a complicated circuit, the proposed structure enjoys from an extremely simple circuit. It also exhibits low input impedance employing negative feedback principal. Of more interest is that, using simple degenerate current mirrors, the differential-mode gain of the proposed CMIA can be electronically varied by control voltage. This property makes it completely free of resistors. The very low number of transistors used in the structure of the proposed CMIA grants it such desirable properties as low-voltage low-power operation, suitability for integration, wide bandwidth etc. SPICE simulation results using the TSMC 0.18-mu m CMOS process model under supply voltage of +/- 0.8 V show a high CMRR of 91 dB and a low input impedance of 291.5 Omega for the proposed CMIA. Temperature simulation results are also provided, which prove low temperature sensitivity of the proposed CMIA.

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate-source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18@mm CMOS technology parameters. Under supply voltage of +/-0.7V and bias current of 5@mA, it can deliver output currents as high as 14mA with THD better than -53dB and extremely high output impedance of 320M@W while consuming only 29@mW. This makes the proposed COS to have ultra large current drive ratio (I"o"u"t"m"a"x/I"b"i"a"s or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to +/-0.9V, it can deliver extremely large output current of +/-24mA corresponding to 3200 current drive ratio while consuming only 42.9@mW and exhibiting high output impedance of 350M@W. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than -45dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only +/-3.29mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR-) of 125dB and 130dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.

This paper proposes a novel tailless ultra low power low voltage high CMRR differential amplifier (D.A.) with rail-to-rail input common mode range (ICMR) based on quasi floating gate (QFG) transistors. For low voltage operation, the tail current source of the conventional D.A. is removed and the resulted lack of CMRR is highly compensated by means of two simple inverters. The required supply voltage is only VGS + VDSsat (with their usual meanings of symbols) which is one VDSsat lower than the required supply voltage for the conventional D.A. Unlike the conventional differential amplifier, slew rate (SR) in the proposed one is not limited by the tail current source and is determined by the amplitude of input signals. The principle of operation, small signal analysis and the formula of the most important parameters of the proposed D.A. are presented. HSPICE simulation results using TSMC 0.18 μm CMOS process parameters and ±0.4 V supply voltage are presented which verify the high performance of the proposed scheme. The simulation results show a rail-to-rail operation and 121 dB CMRR for the proposed tailless differential amplifier. The corner case simulation results are also provided which show a robust performance for the proposed structure. Its unity gain bandwidth product is 72.3 MHz that is 2.31 times larger than that of conventional differential amplifier. Positive and negative SRs are improved by a factor of 7.4 and 3.58 times respectively compared to conventional one. It has also an ultra low power dissipation of 6.89 μW.

In this paper, the simplest possible electronically adjustable transresistance-mode (TRM) instrumentation amplifier (IA) using only eight MOS transistors is presented. Extremely simple structure of the proposed IA leads to a wide bandwidth and robust performance against mismatches and parasitic capacitances. Of more interest is that the differential-mode gain of the proposed IA can be electronically varied by control voltages. Post-layout and pre-layout simulation results based on 0.18[Formula: see text][Formula: see text]m TSMC CMOS parameters are included to confirm the validity of the theoretical analysis. Despite extremely simple structure, its input and output impedances are 1.93 and 1.68[Formula: see text]k[Formula: see text], respectively. Time domain analysis shows that for an input signal of 20[Formula: see text][Formula: see text]A peak to peak, maximum value of THD is 4.5% for different frequencies. Monte Carlo simulation is also carried out, which proves robust performance of the proposed IA against mismatches. The required chip area is only [Formula: see text].

Minaei, Shahram (Dogus Author) -- Conference full title: 2016 39th International Conference on Telecommunications and Signal Processing, TSP : June 27-29, 2016, Vienna, Austria. A New CMOS resistor based current mirror with extremely low voltage requirement at input (in the range of a few mV) and output voltage requirement of about one Vds is presented. The proposed structure combines the advantages of wide input swing, wide output swing, large output impedance, low input impedance and high linearity altogether, which make it attractive for high performance low-voltage and low power applications. Pspice simulations show a very low THD of -42.2dB from a single 0.9V supply in 0.18μm, input impedance of 239Ω, output impedance of 1.2MΩ and power dissipation of only 180μW. Interestingly, the input and output voltage requirements are only 10mV and 0.1V respectively.

In this paper, a CMOS resistor-based current mirror (RBCM) aimed to be used in low-voltage applications is presented. The main features of the proposed current mirror are very low input voltage requirement (a few mV), low output voltage requirement, high output impedance and simple circuitry. The core structure of the proposed RBCM consists of three transistors (excluding bias circuitry) and two low value grounded resistors. The proposed circuit alleviates the need for cascode structures which are conventionally used to boost the output impedance and linearity. SPICE simulations using 0.18[Formula: see text][Formula: see text]m CMOS technology parameters under supply voltage of 0.9[Formula: see text]V are reported which show input and output voltage requirements of 40[Formula: see text]mV and 0.1[Formula: see text]V respectively, low THD of 1.2%, [Formula: see text] of 496[Formula: see text][Formula: see text], [Formula: see text] of 1[Formula: see text]M[Formula: see text], [Formula: see text]3[Formula: see text]dB bandwidth of 181[Formula: see text]MHz and power dissipation of 154[Formula: see text][Formula: see text]W. A high CMRR differential amplifier and a high performance current difference circuit as applications of the proposed RBCM are given. The proposed RBCM is very useful in tackling restrictions of modern technologies such as reduced supply voltage and transistors low intrinsic output impedance.

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8 V and using 0.18 μm CMOS process parameters. The power consumption and the required chip area are only 0.5 mW and 77.4 μm × 70.2 μm, respectively.

In this paper, a novel first-order current-mode (CM) electronically tunable all-pass filter including one grounded capacitor and two dual-output current followers (DO-CFs) is presented. The used DO-CFs are implemented using only 10 MOS transistors granting the proposed CM all-pass filter extremely simple structure. The proposed filter is suitable for integrated circuit (IC) fabrication because it employs only a grounded capacitor and is free from passive component matching conditions. Interestingly the introduced configuration uses minimum number of components compared to other works. It also offers other interesting advantages such as, alleviating all disadvantages associated with the use of resistors, easy cascadability and satisfies all technology requirements such as small sizing, simple realization, low voltage and low power operation. Additionally, the circuit parameters can be easily set by adjusting control voltages. Most favorably, the proposed CM all-pass filter can be simply used as a voltage-mode (VM) all-pass filter with outstanding properties of adjustable gain and tunability. To further show the versatility of the proposed structure a sinusoidal oscillator is also derived from presented CM all-pass filter. Nonideal gain and parasitic impedance effects on developed CM filter are discussed. Finally, simulation results with SPICE program are included to confirm the theory. © 2013 World Scientific Publishing Company.

In this paper a novel fully differential current buffer is introduced. Its novelty originates from two things; 1) special technique applied to reject the input common mode signal and provide high CMRR of 109dB and higher, 2) deliberately arrangement of virtual grounded inputs by a very small but powerful circuit that admirably granted the block the ultra low input impedance of 38mΩ. Furthermore, it consumes low power of 105μW and operates with low voltage supplies of ±0.75V, due to its compact structure. These superb results are verified by HSpice simulation using 0.18μm CMOS technology of TSMC. Monte Carlo simulation of the proposed buffer is also examined that proved its robustness against technology Process (mismatches).

In this paper, a low voltage low power (LPLV) current output stage (COS) with high CMRR is proposed. A novel common mode feedback (CMFB) technique is exploited to provide high CMRR. That is done by summing the main common mode signal and its opposite polarity one which provides over 112dB of CMRR in 0.18µm CMOS technology of TSMC. The circuit operates with very low supply voltages of ±0.5Vand consumes only 145µW power which show good improvement compared to other similar stages in literatures. Monte Carlo simulation of CMRR is also performed and shows its sufficient robustness against mismatches.

In this paper, the implementation of a low-voltage class AB second generation voltage conveyor (VCII) with high current drive capability is presented. Simple realization and good overall performance are the main features of the proposed circuit. Proper solutions and techniques were used to achieve high signal swing and high linearity at Y, X and Z ports of VCII as well as low-voltage operation. The operation of the proposed VCII was verified through SPICE simulations based on TSMC 0.18 mu m CMOS technology parameters and a supply voltage of +/- 0.9 V. The small signal impedance values were 973 Omega, 120 k Omega and 217 Omega at Y, X and Z ports, respectively. The maximum current at the X port was +/- 10 mA with maximum total harmonic distortion (THD) of 2.4% at a frequency of 1 MHz. Considering a bias current (I-B) of 29 mu A and output current at the X port (I-X) of 10 mA, the current drive capability (I-X/I-B) of about 345 was achieved at the X port. The voltage swing at the Z port was (-0.4, 0.4) V. The THD value at the Z port for an input signal with 0.8 V peak-to-peak value and frequency of 1 MHz was 3.9%. The total power consumption was 0.393 mu W. innovation project iRel4.0 ECSEL [876659] This research has been partially founded by the European co-funded innovation project iRel4.0 ECSEL under grant agreement No 876659.