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This paper presents a television (TV) transmitter for wireless video streaming applications in TV white space band. The TV transmitter is composed of a digital TV (DTV) signal generator and a UHF-band RF transmitter. Compared to a conventional high-IF heterodyne structure, the RF transmitter employs a zero-IF quadrature direct up-conversion architecture to minimize hardware overhead and complexity. The RF transmitter features I/Q mismatch compensation circuitry using 12-bit digital-to-analog converters to significantly improve LO and image suppressions. The DTV signal generator produces an 8-vestigial sideband (VSB) modulated digital baseband signal fully compliant with the Advanced Television System Committee (ATSC) DTV signal specifications. By employing the proposed TV transmitter and a commercial TV receiver, over-the-air, real-time, high-definition video streaming has been successfully demonstrated across all UHF-band TV channels between 14 and 69. This work shows that a portable hand-held TV transmitter can be a useful TV-band device for wireless video streaming application in TV white space.

A CMOS ultra-high frequency-band RF transceiver based on 8-phase harmonic rejection mixer (HRM) architecture with an integrated fractional-N PLL synthesizer is presented for television white space applications. A divide-by-2 and a phase interpolator (PI) circuit are used to generate the 8-phase LO signals for the HRM. The synthesizer output frequency is two times higher than the desired band frequency. The PI is tunable to allow 7-bit calibration of 45° and 135° LO phases. A systematic 2-D calibration scheme that is applicable to both the receiver and transmitter is described. It is demonstrated that only 45° and 135° LO phase calibration is sufficient to minimize the third and fifth harmonic components. Implemented in 0.18- $\mu$ m CMOS, the RF transceiver covers 470–806 MHz, achieving the third and fifth harmonic suppressions below −48 and −56 dBc at the receiver, and the harmonic emission below −51 dBc at the transmitter.

A 28GHz RF transmitter is designed in 65nm CMOS for 5G millimeter-wave radio applications. The transmitter is based on a direct-conversion quadrature up-conversion architecture for achieving small silicon area and low power dissipation. The image suppression is improved by adopting I/Q LO mismatch calibration at the LO driving buffer of mixer. The power amplifier is designed in a differential type with cross-coupled neutralized capacitors for stability and reverse-isolation improvement. Combined schematic and EM simulation results show that the transmitter gives the power gain of 37 dB, OP1dB of +5.8 dBm, and P sat of +11.6 dBm. The total transmitter consumes 111 mW from a 1.2 V supply and occupies 1.78 mm2.

This paper presents a direct-conversion zero-IF receiver front-end circuit for 28-GHz 5G mobile communications. The RF receiver is composed of LNA, quadrature downconversion mixer, wideband 50-ohm driving buffer, and I/Q generation LO buffer. The low-noise amplifier is designed in two-stage, in which the first cascode stage performs the single-to-differential conversion by using a transformer load. The mixer is a gilbert-cell active type. The 50-ohm driving buffer performs the differential-to-single conversion for test interface purpose. An external LO signal is fed to a RC polyphase filter, and splits into differential I/Q LO signals. Designed in 65nm CMOS process, extensive electromagnetic simulations after chip layout are carried out to evaluate the performances. The full receiver dissipates 90 mW from a 1.2-V supply. The Rx full-path gives the gain of +27.4 dB, noise figure of 4.6 dB, 1-dB input compression point of -38 dBm, and the baseband channel bandwidth of 1 GHz. The die size is 2 mm2including RF pads.

A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is 490 μA from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by 7.5 dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.

The second-order interaction effect in a field-effect transistor (FET) differential amplifier is analyzed using the Volterra series analysis method. The analysis results reveal that the second-order interaction is inherent in the fully differential amplifier structure, and thus can never be cancelled out. In contrast, it is found that the second-order interaction is possibly cancelled out by adding source degeneration impedance in the pseudodifferential amplifier (PDA) structure. In addition, the second-order interaction cancellation condition in the PDA can be made more robust and wider over the input signal swing by adopting the derivative superposition (DS) method. By combining the second-order interaction cancellation technique and the DS technique, a differential source degenerated DS method is proposed for linearizing FET differential amplifiers. A 2-GHz differential amplifier based on the proposed structure is designed for a power amplifier driver in an RF transmitter. Fabricated in ${\hbox{0.13-}}\mu{\hbox{m}}$ CMOS, it operates from a 1.2-V supply with the power dissipation of 30.2 mW. Measurement results show that it achieves $+{\hbox{30.4 dBm}}$ of peak output third-order intercept point, 43 dBc of C/I at 0-dBm output power, $+{\hbox{9.7 dBm}}$ of output-referred P1dB, and $+{\hbox{10.6 dB}}$ of power gain.

A sliding-IF RF receiver front-end is designed in 65 nm CMOS general process for Bluetooth low-energy applications. For low power consumption, the receiver front-end circuits are designed with a 1-V supply voltage. Simulations show that the receiver has a 55.5 dB full-path maximum gain, and −43.5 dBm input-referred P 1dB while dissipating only 2.2 mW. At the maximum gain, the noise figure is 3.2 dB, which corresponds to the sensitivity of −98.8 dBm when the minimum required SNR of a demodulator is 12 dB.

A fractional-N PLL synthesizer is designed in 65 nm CMOS general process for Bluetooth low-energy applications. For low-power consumption, the PLL synthesizer is designed in a single 1-V supply. The tuning range of PLL Synthesizer is 1.9–2.7 GHz to cover the ISM band for 1/5-fRF sliding-IF receiver. The simulated VCO phase noises at 1 MHz offset are −110 and −120 dBc/Hz at 2.7 and 1.9 GHz, respectively. With a fast VCO frequency calibration process included, the total lock time of the synthesizer is 12 μs. The synthesizer dissipates 3 mW from 1 V supply voltage.

This paper describes low-voltage and low-power design of a CMOS RF receiver front-end circuit for MICS applications. The direct-conversion RF receiver is composed of a single-ended cascode LNA, single-to-differential converting gm-stage, quadrature passive mixer with 25% LO duty cycle, and transimpedance amplifier. Extensive circuit simulations show that the receiver has the maximum conversion gain of 45 dB, the input-referred P1dB of −34.8 dBm, and the noise figure of 2.6 dB, while dissipating 1.4 mW from a 1-V supply.

A compact bandpass filter (BPF) using a very short capacitively coupled resonator exhibits wide-stopband characteristics. It is based on two

A 28GHz CMOS phased array T/R circuit is designed for 3-dimensional beamforming system in 5G millimeter-wave communication applications. The T/R circuit integrates a phase shifter, a digital step attenuator and a SP8T switch. It provides 64-state attenuations in 0.5dB step via 6-bit attenuator circuit, and 32-state phase shifts in 11.25° step via 5-bit phase shift circuit, and overall a 14dB insertion loss, 7.6dBm input-referred P1dB.

A 2.59GHz self-interference cancellation (SIC) circuit is presented for in-band full-duplex radio. The SIC circuit is based on an analog vector modulator whose output can automatically track the time-varying self-interference signal through an analog LMS algorithm based weight calculation circuit. By adding a variable gain stage after the vector modulator, the total dynamic range is significantly widened so that the SIC can deal with large Tx power variation and/or Tx-to-Rx attenuation. Implemented in 16.4 × 11.9 cm2 printed circuit board, the circuit achieves the cancellation ratio of 39.2 dB and 39.4 dB for 5MHz and 10MHz bandwidth 16-QAM signal, respectively. Also, the dynamic range is increased from 22 dB to 40 dB by properly setting the variable gain.

An RF energy detector for spectrum sensing in TV white space transceiver is presented. It is based on an RF active filtering technique that comprises a low-noise amplifier with a frequency-translation high-pass filtering feedfoward loop, which attenuates the unwanted sideband energy and only passes the wanted band energy. Unlike the conventional architecture, a new architecture that can attenuate both sidebands at the same time is proposed. A simplified system modeling method is presented to assess the non-ideality effects on the RF energy detector performances. System behavioral simulations demonstrate that the proposed architecture can be instrumental for realizaing a RF energy detector circuit in CMOS.

A broadband suspended substrate filter is proposed and implemented using dual-mode resonator aiming at transmitting the signals in the passband of 10–18 GHz. It is composed of two quarter-wavelength resonators and inductor. The inductor is a short-circuited stub. After optimization of this filter, a good bandpass behavior with 10 transmission poles is theoretically realized and experimentally confirmed. Within the whole BPF passband, the return loss is found better than 10 dB, and the insertion loss is less than 1.9 dB. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26070

A 54-862-MHz single-chip CMOS transceiver with a single LC voltage-controlled oscillator (VCO) fractional-N synthesizer is developed for TV-band white-space communications and cognitive radio applications. The transceiver is based on a single-conversion zero-IF architecture with integrated harmonic filtering capability. A combined harmonic rejection mixer and coarse RF tracking filter significantly lessens the in-band harmonic emission problem in the transmitter, as well as the harmonic mixing problem in the receiver. A fractional-N phase-locked loop (PLL) with only a single LC VCO and a wideband multimodulus local oscillator (LO) generator seamlessly covers the entire band. A wideband semi-dynamic divide-by-1.5 circuit is adopted in the LO generator to reduce the VCO tuning range requirement by 25 %. A pseudoexponential capacitor bank structure in the LC VCO substantially reduces the KVCO and fstep variations across the total band, which is beneficial for maintaining the PLL loop stability and dynamics over the wide band. The transceiver is implemented in 0.18-μ m CMOS, and operates with a single 1.8-V supply. The transmitter delivers a nominal output power of -3 dBm, and exhibits OP1 dB of >; +6.4 dBm, OIP3 of >; +15.9 dBm, and error vector magnitude (EVM) of

Autocalibration of VCO frequency and loop gain is an essential process in PLL frequency synthesizers. In a wide tuning-range fractional-NPLL frequency synthesizer, high-speed and high-precision automatic calibration is especially important for shortening the lock time and improving the phase noise. This paper reviews the design issues of the PLL auto-calibration and discusses on the limitations of the previous techniques. A very simple and efficient auto-calibration method based on a high-speed frequency-to-digital converter (FDC) is proposed and verified through simulations. The proposed method is highly suited for a very wide-bandΔΣfractional-NPLL.

A 2.4-GHz CMOS on-off keying (OOK) transmitter is developed for applications that require high data rate over 10Mbps in the area of wireless body area network (WBAN) and medical implant communication service (MICS). A novel analog pulse-shaping circuit for reducing power consumption and circuit complexity is employed for the OOK transmitter. Fabricated in 0.13µm CMOS, the transmitter core excluding the 50 ohm driving buffer dissipates 0.95mW from 1.2-V supply. Measurement shows that it can support the data rate up to 22Mbps. With the pulse-shaping capability enabled, the transmitter output spectrum shows successful suppression of the sidelobe power below -42dBc at 100MHz offset from the center frequency.

A CMOS transceiver is designed and fabricated for implantable cardioverter telemetry service. For the image rejection, a complex filter is used in the receiver instead of the conventional image rejection mixer type. Low power consumption is essential for the implantable medical service, thus the RF blocks such as the low noise amplifier, voltage controlled oscillator, and frequency synthesizer are designed by focusing on the low power operation. The transceiver is implemented in 0.18-µm CMOS process, and operates with a single 1.8-V supply. The sensitivity is −85 dBm. The phase noise characteristic of frequency synthesizer is −87 dBc/Hz at 10 kHz offset frequency. Maximum output power of the transmitter is −2.8 dBm. The transceiver achieves 500 kbps maximum data rate with 22 mW power consumption. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2580–2582, 2014

An active resistor-capacitor low-pass filter with simultaneously programmable high-end and low-end cutoff frequencies is presented for IEEE 802.22 cognitive radio transmitter applications. Transfer function analysis shows that the integrator frequency of a dc offset cancellation block should be tuned inversely proportional to the open-loop gain to maintain the low-end cutoff frequency at a constant value. Realized in a 0.18- ?m complementary metal-oxide-semiconductor, the low-end cutoff frequency is successfully tuned between 740 Hz and 10 kHz over the 30-dB gain variation. Measured results show that the gain is tuned from -16.3 to +13.9 dB, and the high-end cutoff frequency is tuned from 2.1 to 6.04 MHz, while drawing 4.5 mA from a 1.8-V supply.

A high-speed pulse-swallow frequency divider suitable for ΔΣ fractional-N synthesizers is proposed. The proposed structure employs the retiming scheme for the modulus control signal to extend the timing margin, thus remarkably increasing the maximum operating speed. Moreover, unlike the conventional structure, the modulus control signal is set and reset by a single triggering signal to eliminate the unwanted offset at the total division ratio. It simplifies the interface logic between the divider and the ΔΣ modulator in ΔΣ fractional-N PLL's. Simulation results show that the proposed divider provides over three times faster operating speed than the conventional one. The proposed divider has been successfully verified in CMOS RF ΔΣ fractional-N frequency synthesizers.

A compact circuit model for five-port on-chip transformer balun is presented. Compared to the conventional model, the proposed model is simpler without any accuracy degradation and ensures faster convergence time, which in turn enables flexible RF circuit design optimization. The validity of the proposed model is confirmed through extensive EM simulations and measurements.

A novel compact model for a five-port transformer balun is proposed for the efficient circuit design of hybrid balun. Compared to the conventional model, the proposed model provides much faster computation time and more reasonable values for the extracted parameters. The hybrid balun, realized in 0.18 ㎛ CMOS, achieves 2.8 ㏈ higher gain and 1.9 ㏈ lower noise figure than its passive counterpart only at a current consumption of 0.67 ㎃ from 1.2 V supply. By employing the hybrid balun, a differential zero-IF receiver is designed in 0.18 ㎛ CMOS for IEEE 802.15.4 ZigBee applications. It is composed of a differential cascode LNA, passive mixers, and active RC filters. Comparative investigations on the three receiver designs, each employing the hybrid balun, a simple transformer balun, and an ideal balun, clearly demonstrate the advantages of the hybrid balun in fully differential CMOS RF receivers. The simulated results of the receiver with the hybrid balun show 33 ㏈ of conversion gain, 4.2 ㏈ of noise figure with 20 ㎑ of 1/f noise corner frequency, and -17.5 ㏈m of IIP3 at a current consumption of 5 ㎃ from 1.8 V supply.

A pseudo-exponential capacitor bank structure is proposed to implement a wide-band CMOS LC voltage-controlled oscillator (VCO) with linearized coarse tuning characteristics. An octave bandwidth VCO employing the proposed 6-bit pseudo-exponential capacitor bank structure has been realized in 0.18-mum CMOS. Compared to a conventional VCO employing a binary weighted capacitor bank, the proposed VCO has considerably reduced the variations of the VCO gain (K VCO) and the frequency step per a capacitor bank code (f step/code) by 2.7 and 2.1 times, respectively, across the tuning range of 924-1850 MHz. Measurement results have also shown that the VCO provides the phase noise of - 127.1 dBc/Hz at 1-MHz offset for 1.752-GHz output frequency while dissipating 6 mA from a 1.8-V supply.

Frequency generation and synthesis circuits are ubiquitous building blocks in communication, sensing, and imaging systems. This session covers the latest advances in frequency synthesizers and VCOs in GHz and THz frequency ranges. The session begins with a CMOS frequency synthesizer operating above 0.5THz and a 28GHz coupled PLL for mm-Wave 5G applications. The session also presents two GHz-range PLLs, which include a PLL-DLL cascaded structure operating over a wide bandwidth and achieving low phase noise and a high-performance BiCMOS fractional-N synthesizer for backhaul applications. Two VCOs are presented next. The first VCO is a low-power complementary VCO with a low flicker noise corner. This is followed by a 190GHz VCO with very wide tuning range and a time-interleaved ring VCO with a low 1/f3 noise corner. The last two papers describe an injection-locked frequency-locked loop with a self-calibrated locking algorithm and a 2GHz 244fs-resolution digital-to-time converter.

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65 %. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in 0.18-μm CMOS, the PLL covers 154 ~ 303 MHz (VHF-III), 462 ~ 911 MHz (UHF), and 1441 ~ 1887 MHz (L1, L2) with two VCO’s while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

A semidynamic frequency divide-by-1.5 MMIC comprises a tunable polyphase filter, tunable image-rejection mixer, and a static divide-by-2 in the feedback path. Wideband suppression of unwanted tones is achieved by employing a tunable image-rejection mixer and a tunable single-stage polyphase filter. Implemented in GaInP/GaAs HBT technology, the divide-by-1.5 MMIC operates over the input frequency range of 4.5 to 9.2 GHz with better than -20 dBc suppressions of tones, while dissipating 29 mA from 4.1 V supply.

An inductor library for efficient low cost RFIC design has been developed based on a standard digital 0.18 CMOS process. The developed library provides four structural variations that are most popular in RFIC design; standard spiral structure, patterned ground shield(PGS) structure to enhance quality factor, stacked structure to enable high inductance values in a given silicon area, multilayer structure to lower series resistance. Electromagnetic simulation, equivalent circuit, and parameter extraction processes have been verified based on measurement results. The extensive measurement and simulation results of the inductor library can be a great asset for low cost RFIC design and development.

A 40GHz PLL synthesizer is designed in 65nm CMOS for a 60GHz sliding-IF RF transceiver for IEEE 802.11ad applications. For wide locking range, ILFD employs a 5-bit switched capacitor array and a inductive peaking at the injection FET. The ILFD's locking range is wider than the VCO's tuning range, which ensures the PLL can safely lock across the VCO's full tuning range. Also, a tuned buffer with a boosted Q load is employed to minimize unwanted interaction between the VCO and ILFD's operating frequencies, which also helps widen the PLL's locking range. The PLL synthesizer is designed in 65nm CMOS and its die area is 1.0×1.1mm2.

This paper presents a new push-push voltage-controlled oscillator (VCO) technique that extracts a second harmonic output signal from a capacitive common node in a negative-gm oscillator topology. The generation of the second harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing: 1) significant voltage clipping and 2) different rise and fall times during the switching operation of the core transistors. Comparative investigations show the technique is more power efficient in the high-frequency region than a conventional push-push technique using an emitter common node. A prototype 17-GHz VCO realized in GaInP/GaAs HBT technology produces an output power of -6dBm and a phase noise of -110.4dBc/Hz at 1-MHz offset, which is equivalent to a VCO figure-of-merit of -184.3dBc/Hz, while drawing 4.38 mA from a 3.0-V supply

This paper presents a dual-band voltage-controlled oscillator (VCO) that can be reconfigured between 6- and 9-GHz frequency bands. It comprises a 6-GHz LC-tuned VCO, two 1/2 dividers, two mixers, and two 3-GHz notch filters. The 9-GHz output is generated based on the analog frequency multiplication method by mixing the 6-GHz VCO output with its divide-by-two signal. The VCO, implemented in a 0.18-/spl mu/m SiGe BiCMOS technology, achieves a fast reconfiguration time of 3.6 ns. The measured VCO phase noises are -106 and -104 dBc/Hz at 1-MHz offset for 6- and 9-GHz modes, respectively, while draining 10.8 mA from a 1.8-V supply.

A UHF/VHF LNA-less receiver is designed in 65nm CMOS for TV white-space long-range wireless sensor network applications. Noise cancelling and blocker-tolerant architecture is adopted for wide-band low-noise performance without a narrow-band LNA. The receiver consists of main- and auxiliary-path passive mixers, TIA, harmonic recombination block, and baseband filters, all of which are configured for noise cancellation. Operating between 80MHz and 1.15GHz, noise figure with 1GHz LO frequency is 1.9 dB. Blocker noise figure with 80MHz-offset 0dBm-blocker is 3.2 dB.

Recent studies showed that conventional approaches being used to solve problems imposed by hard-wired metal interconnects will eventually encounter fundamental limits and may impede the advance of future ultralarge-scale integrated circuits (ULSls). To surpass these fundamental limits, we introduce a novel RF/wireless interconnect concept for future inter- and intra-ULSI communications. Unlike the traditional "passive" metal interconnect, the "active" RF/wireless interconnect is based on low loss and dispersion-free microwave signal transmission, near-field capacitive coupling, and modem multiple-access algorithms. In this paper we address issues relevant to the signal channeling of the RF/wireless interconnect and discuss its advantages in speed, signal integrity, and channel reconfiguration. The electronic overhead required in the RF/wireless-interconnect system and its compatibility with the future ULSI and MCM (multi-chip-module) will be discussed as well.

A forward body biasing (FBB) technique is employed by an extended true-single-phase-clock (E-TSPC) divide-by-2 circuit in 0.25 mu m CMOS for an efficient on-chip control of power and speed. By applying the forward body bias voltage of 0.4 V, the maximum operating frequency is improved by 78% while the current dissipation is increased only by 21%. As a result, the divider figure-of-merit is improved by 46%. The phase noise however is not significantly affected by the forward body biasing. We believe that the FBB technique can be an efficient means for on-chip scaling of speed and power in E-TSPC RF frequency divider circuits.

In a low dropout (LDO) linear regulator whose reference voltage is supplied by a bandgap reference, double stacked diodes increase the effective junction area ratio in the bandgap reference, which significantly lowers the output spectral noise of the LDO. A low noise LDO with the area-efficient bandgap reference is implemented in 0.18 8 μm CMOS. An effective diode area ratio of 105 is obtained while the actual silicon area is saved by a factor of 4.77. As a result, a remarkably low output noise of 186nV/sqrt(Hz) is achieved at 1 kHz. Moreover, the dropout voltage, line regulation, and load regulation of the LDO are measured to be 0.3 V, 0.04%/V, and 0.46%, respectively.

A wideband complementary metal oxide semiconductor (CMOS) semidynamic frequency divide-by-3 covering more than two octave bandwidths is presented. The wideband operation without requiring a quadrature signal source is realized by employing a three-stage RC polyphase filter. The transfer function analysis on Type-II two- and three-stage polyphase filters is performed to provide analytic solutions of the peak phase error and peak attenuation. Implemented in 0.18 mum CMOS, the divide-by-3 operates over the input frequency range between 0.6 and 2.7 GHz while dissipating 15 mA from a 1.8 V supply.

A semidynamic frequency divide-by-1.5 circuit comprises an image-rejection mixer and a static divide-by-2 in its feedback path. Wideband suppression of unwanted tones is achieved by employing a tunable image-rejection mixer and a tunable single-stage polyphase filter. Implemented in GaInP/GaAs heterojunction bipolar transistor technology, the divide-by-1.5 operates over the input frequency range of 4.5 to 9.2GHz with better than -20-dBc suppressions of 1/3timesfin and fin components, while dissipating 29 mA from a 4.1-V supply

We have developed a low-voltage, low-power Ku-band microwave monolithic integrated circuit (MMIC) downconverter using InGaP-GaAs heterojunction bipolar transistor technology. It consists of a preamplifier, a double-balanced mixer, and an L-band wideband intermediate-frequency (IF) amplifier. The downconverter achieves a conversion gain of 31 dB, with a gain flatness within /spl plusmn/ 1 dB, and an output-referred 1-dB compression power (P/sub 1dB,OUT/) of +2.5dBm. This downconverter dissipates 33mA from a 3-V supply. We believe that the operating voltage and power consumption are lower than those of previously published Ku-band MMIC downconverters.

A two-point tuning VCO with switchable secondary tuning gain K VCO2 is designed in 65㎚ CMOS for a two-point modulation PLL-based phase modulator that is to serve as phase-modulating part of a quad-band GSM/GPRS/EDGE polar transmitter. The two-point tuning VCO employs two varactor banks for dual tuning capability. The second varactor bank is a differentially tuned structure and its gain K VCO2 is switchable to minimize its variation for maintaining optimum second-point modulation gain. Fabricated in 65㎚ CMOS, the VCO draws 8 ㎃ from 2 V supply. It covers the 2930 ? 4150 ㎒. The phase noise is -142㏈Bc/㎐ at 10㎒ offset for 3.9 ㎓ output frequency. The silicon area of the VCO and accompanying dividers is 810 x 600 ㎛².

This paper discusses the design considerations for CMOS transceiver targeting for cognitive radio based TV white space applications. With the total frequency band ranging from 54 to 862 MHz, not only harmonic distortions in RF transceiver but also wideband LO generation in frequency synthesizer needs to be carefully addressed. We present that the dual-path direct-conversion architecture adopting on-chip harmonic rejecting scheme significantly lowers the harmonic emission problem in the transmitter and the harmonic mixing problem in the receiver. Also, the entire band is covered by a wideband LO generation block combined with a single LC-VCO synthesizer. For the energy detection for the spectrum sensing, the feedforward RF filtering scheme with the center frequency and bandwidth simultaneously tunable is presented.

An extended true-single-phase-clock (E-TSPC) dual-modulus prescaler with a division ratio of 2 and 3 employs the forward body biasing (FBB) technique for achieving efficient on-the-fly speed and power control. The circuit is implemented in 0.25 urn CMOS. With the forward body bias voltage of 0.7 V applied to N- and P-FET's, the maximum operating frequency is improved by 80 and 87 % in the divide-by-2 and −3 modes, respectively, while the current dissipation is increased by 27 and 28 % As a result, the figure-of-merit of the prescaler is enhanced by 42 and 46 % for the divide-by-2 and 3 modes, respectively. The phase noise however does not show significant degradation at the FBB voltage less than 0.7 V. We believe that the FBB technique can be an efficient means of on-the-fly speed and power scaling in CMOS RF E-TSPC prescaler circuits.

A CMOS single-chip transceiver IC is developed for IEEE 802.22 cognitive radio applications. Over the 54 to 862 MHz ultra wideband, the in-band harmonic distortions of the transmitter and the unwanted harmonic mixing of the receiver are effectively suppressed by exploiting the dual-path direct-conversion architecture. A seamless coverage of the full band is achieved by employing a fractional-N PLL with a single LC VCO and a multi-modulus LO generator. Implemented in 0.18 µm CMOS, the receiver achieves 110 dB gain dynamic range, ≪ 8.5 dB noise figure, and ≫ −11 dBm IIP 3 at the LNA bypass mode. The transmitter delivers −3 dBm output power with OP 1dB and OIP3 greater than +6.4 dBm and +15.9 dBm, respectively. On-chip calibration circuits suppress the image and carrier leakage components below −41 dBc across the total band.

A wideband CMOS low noise amplifier covering 2.3–2.7 GHz is designed for WLAN/WiMAX applications. Continuously tuned wideband characteristics are obtained by employing a novel tunable input matching circuit that is configured as back-to-back connected MOS varactors. The back-to-back structure significantly increases the capacitance variation ratio compared to the conventional single varactor structure. The LNA with the varactor tuned input capacitance is designed as a fully differential cascode type in a 0.13 μm CMOS process. It covers the frequency band between 2.3 and 2.7 GHz, and obtains a gain of 26.2 dB, a noise figure of 0.98 dB, IIP3 of −14.6 dBm across the total band. It draws 14.8 mA from a 1.2 V supply voltage.

A low-power CMOS on-off keying (OOK) transmitter employing a triangular pulse shaping scheme is presented. The proposed pulse shaping circuit is based on a current-reused common-source stage, whose gain is controlled by modulating the gate-source voltage in a triangular form. The triangular control signal is generated by an opamp-based integrator. The proposed pulse shaping scheme can effectively support variable data rate. A 3.5-GHz OOK transmitter circuit adopting the proposed pulse shaping scheme is designed in a 0.13 μm CMOS process. It successfully modulates digital data from 100 kbps to 10 Mbps and delivers an output power of +2.5 dBm. The total current consumption is 4.17 mA from a 1.2 V supply voltage, of which only 0.57 mA is dissipated at the transmitter core excluding the output buffer.

A resistively degenerated differential amplifier is linearized by using a source-coupled auxiliary FET pair. The structure does not lower the effective g3 of the degenerated auxiliary FET pair while it efficiently cancels the second harmonic feedback component. Realized in 0.18-mum CMOS, the proposed differential amplifier achieves 9.8 dB of power gain, +7.7 dBm of output P1dB, and +25.8 dBm of peak OIP3. The maximum output power level with OIP3 greater than +20 dBm is extended by 7 ~ 10 dB compared to the conventional structure adopting a source-decoupled auxiliary FET pair. The results prove that the proposed degeneration configuration is suitable for linearizing a resistively degenerated CMOS differential amplifier.