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Advanced bottom electrode contact (BEC) scheme was successfully developed for fabricating reliable high density 64 Mb PRAM by using ring type contact scheme. This advanced ring type BEC scheme was prepared by depositing very thin TiN films inside a contact hole, and then core dielectrics was uniformly filled into the TiN-deposited contact hole. Using this novel contact scheme, it was possible to reduce a reset current with low set resistance, and also maintain a uniform cell distribution. Thus, it is clearly demonstrated that the ring type BEC technology can exhibit strong feasibility of high density 256 Mb PRAM and beyond.

A novel 8F/sup 2/ cell structure for high density magnetic random access memory (MRAM) and its operating characteristics are proposed. In this new scheme, we formed bottom electrode contact (BEC) through twin metal lines (MLs) and a magnetic tunnel junction (MTJ) was located just on the BEC for the reduction of cell size. From the results of simulation and experiment, we have confirmed that the generated magnetic field in the new scheme is more uniform than that in the conventional scheme with a negligible reduction of writing field strength. We adopted a self-aligned BEC process to prevent electrical shorting between ML and BEC. To avoid electrical shorting and improve the magnetic properties of MTJs, a chemical mechanical polishing (CMP) process was adopted before MTJ deposition. As a result, we confirmed the feasibility of high-density 1T1MTJ MRAM, composed of 8F/sup 2/ cells with optimal MTJ characteristics.

The DRAM process technology has been on the leading edge of semiconductor technology, and the density of DRAM has been quadrupled every three years. 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) was successfully manufactured and much attention is now given to the process technology for 4 Gb DRAM based on 0.15 /spl mu/m technology node or smaller than 0.15 /spl mu/m technology node. 0.15 /spl mu/m technology node is considered to be transition node between 0.18 /spl mu/m which KrF lithography is used on 200 mm wafers and 0.13 /spl mu/m node in which ArF lithography will be used on 300 mm wafers. In this paper, key process and integration technologies for 0.15 /spl mu/m DRAM technology node are developed in order to satisfy both 0.18 /spl mu/m technology node and 0.13 /spl mu/m node. The process and integration technologies employed in 0.15 /spl mu/m technology node are verified with an experimental 16 Mb DRAM.