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Electroencephalography (EEG) systems have been used for assessing cognitive function in dementia for several decades. Studies have demonstrated that EEG in Alzheimer's disease (AD) patients is generally characterized by significant and specific increases in delta and theta power, a decrease in alpha power, and a decrease in the coherence of the fast bands between different brain areas linked by long corticocortical fibers. Posterior EEG characteristics in dementia with Lewy bodies (DLB) allowed discrimination of DLB from AD and controls with high accuracy. Traditional EEG systems require a long application time and discomfort, which limited its use in dementia patients. Alternative tools for assessing cognition may be simple, low-cost, and mobile medical devices such as wireless and mobile EEG (wmEEG) sensor platforms with flexible electronics and stretchable electrode sheets that could be compatible with long-term EEG monitoring even in dementia patients. In this study, we review the utility of EEG in reflecting cognitive function and the prospects for clinical application of wmEEG monitoring for detecting early dementia and discriminating subtypes of dementia effectively and objectively assessing longitudinal cognitive changes. Repeated and longitudinal documentation of EEG using wmEEG will contribute to detection of specific sleep/wake EEG patterns for patients with sleep and wake-related problems related to dementia.

Differential amplifiers based on organic thin-film transistors (OTFTs) are attractive for monitoring human vital signs because of their signal amplification and noise elimination capabilities. However, substantial variations in OTFTs lead to the degradation of signal processing performance in circuits and restrict the development of organic differential amplifiers capable of recording weak physiological potentials. Here, we report a 2-μm-thick ultraflexible organic differential amplifier capable of processing physiological signals with high signal integrity and sensitivity. Our approach uses a circuit design and compensation technique that suppress the mismatch among OTFTs to less than a few percent. This leads to a common-mode noise attenuation factor below −12 dB, even during bending to ~50 μm. Using our flexible amplifier, we monitor electrocardiogram signals, where the power of 60 Hz electrical harmonic noise was reduced ~60 times during amplification, yielding electrocardiogram signals with a signal-to-noise ratio of 34 dB. An ultraflexible organic differential amplifier, which is only 2 μm thick and can conform to a person’s skin, can be used to record electrocardiograms with a signal-to-noise ratio of 34 dB.

This paper presents a low-energy 64-Kb eight-transistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 8T SRAM cell size is $0.291 \times 1.457\,\,\mu \text{m}^{2}$ . The test chip exhibits 0.48-V operation at an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme.

One-dimensional metal nanowires offer great potential in printing transparent electrodes for next-generation optoelectronic devices such as flexible displays and flexible solar cells. Printing fine patterns of metal nanowires with widths 90%. In this method, the AgNW dispersion, which is swept by a glass rod, is spontaneously deposited to the hydrophilic areas patterned on a hydrophobic-coated substrate. The alignment and accumulation of AgNWs at the pattern periphery are enhanced by employing a high sweeping rate of >3.2 mm s-1, improving electrical conductivity and pattern definition. The more aligned and more accumulated AgNWs lower the sheet resistance by a factor of up to 6.8. In addition, a high pattern accuracy ?3.6 ?m, which is the deviation from the pattern designs, is achieved. Quantitative analyses are implemented on the nanowire alignment to understand the nanowire geometry. This fine-printing method of the AgNW electrodes will provide great opportunities for realizing flexible and high-performance optoelectronic devices.

The capacity of embedded memory on LSIs has kept increasing. It is important to reduce the leakage power of embedded memory for low-power LSIs. In fact, the ITRS predicts that the leakage power in embedded memory will account for 40% of all power consumption by 2024 [1]. A spin transfer torque magneto-resistance random access memory (STT-MRAM) is promising for use as non-volatile memory to reduce the leakage power. It is useful because it can function at low voltages and has a lifetime of over 1016 write cycles [2]. In addition, the STT-MRAM technology has a smaller bit cell than an SRAM. Making the STT-MRAM is suitable for use in high-density products [3–7]. The STT-MRAM uses magnetic tunnel junction (MTJ). The MTJ has two states: a parallel state and an anti-parallel state. These states mean that the magnetization direction of the MTJ’s layers are the same or different. The directions pair determines the MTJ’s magneto- resistance value. The states of MTJ can be changed by the current flowing. The MTJ resistance becomes low in the parallel state and high in the anti-parallel state. The MTJ potentially operates at less than 0.4 V [8]. In other hands, it is difficult to design peripheral circuitry for an STT-MRAM array at such a low voltage. In this paper, we propose a counter-based read circuit that functions at 0.4 V, which is tolerant of process variation and temperature fluctuation.

This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise-tolerant instantaneous heartbeat detector. The novelty of this work is the combination of the non-volatile MCU for normally off computing and a noise-tolerant-QRS (heartbeat) detector to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a non-volatile flip-flop and a 6T-4C NVRAM are used. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heartbeat detector uses coarse-fine autocorrelation and a template matching technique. Accurate heartbeat detection also contributes system-level power reduction because the active ratio of ADC and digital block can be reduced using heartbeat prediction. Measurement results show that the fully integrated ECG-SoC consumes 6.14 $\mu$ A including 1.28- $\mu$ A non-volatile MCU and 0.7- $\mu$ A heartbeat detector.

We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines in write operations. Through minor modifications, this scheme can be implemented for existing SRAMs. It has high speed, and it can be implemented in a very small area overhead. The generated fingerprint mainly reflects threshold voltages of load transistors in the bitcells. We fabricated test chips in a 65-nm process and obtained 12,288 sets of unique 128-bit fingerprints, which are evaluated in this paper. The failure rate of the IDs is found to be 2.1 × 10−12. key words: SRAM, chip ID, physical unclonable function (PUF)

This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. We implemented a 256-Kb DW8T SRAM and a half-VDD generator with a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600mV and improves the average VDDmin by 367mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%.

We propose a novel substrate-bias control scheme for an FD-SOI SRAM that suppresses inter-die variability. The proposed circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 486-kb 6T SRAM operates at 0.42V, in which an FS corner can be compared as much as 0.14V or more.

This paper presents a novel disturb mitigation scheme which achieves low-energy operation for a deep sub-micron 8T SRAM macro. The classic write-back scheme with a dedicated read port overcame both half-select and read-disturb problems. Moreover, it improved the yield, particularly in the low-voltage range. The conventional scheme, however, consumed more power because of charging and discharging all write bitlines in a sub-block. Our proposed scheme reduces the power overhead of the write-back scheme using a floating write bitline technique and a low-swing bitline driver (LSBD). The floating bitline and the LSBD respectively consist of a precharge-less CMOS equalizer (transmission gate) and an nMOS write-back driver. The voltage on the floating write bitline is at an intermediate voltage between the ground and the supply voltage before a write cycle. The write target cells are written by normal CMOS drivers, whereas the write bitlines in half-selected columns are driven by the LSBDs in the write cycle, which suppresses the write bitline voltage to VDD - Vtn and therefore saves the active power in the half-selected columns (where Vtn is a threshold voltage of an nMOS). In addition, the proposed scheme reduces a leakage current from the write bitline because of the floating write bitline. The active leakage is reduced by 33% at the FF corner, 125°C. The active energy in the write operation is reduced by 37% at the FF corner. In other process corners, more writing power reduction can be expected because it depends on the Vtn in the LSBD. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The test chip with the proposed scheme respectively achieves 1.52-µW/MHz writing energy and 72.8-µW leakage power, which are 59.4% and 26.0% better than those of the conventional write-back scheme. The total energy is 12.9 µW/MHz (12.9 pJ/access) at a supply voltage of 0.5V and operating frequency of 6.25MHz in a 50%-read/50%-write operation.

This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-Kb blocks in which 8-Kb data can be compared in 130.0ns. The proposed scheme reduces energy consumption in data comparison to 1/418, compared to that of a parallel cyclic redundancy check (CRC) circuit.

This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3ns at 1.2V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner. By applying the proposed scheme to transactional memory, the number of write back cycles is possibly reduced by 98.7% compared with the conventional memory system.