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The continuous quest for performance pushed processors to incorporate elements such as multiple cores, caches, acceleration units, or speculative execution that make systems very complex. On the other hand, these features often expose unexpected vulnerabilities that pose new challenges. For example, the timing differences introduced by caches or speculative execution can be exploited to leak information or detect activity patterns. Protecting embedded systems from existing attacks is extremely challenging, and it is made even harder by the continuous rise of new microarchitectural attacks (e.g., the Spectre and Orchestration attacks). In this article, we present a new approach based on count-min sketches for detecting microarchitectural attacks in the microprocessors featured by embedded systems. The idea is to add to the system a security checking module (without modifying the microprocessor under protection) in charge of observing the fetched instructions and identifying and signaling possible suspicious activities without interfering with the nominal activity of the system. The proposed approach can be programmed at design time (and reprogrammed after deployment) in order to always keep updated the list of the attacks that the checker is able to identify. We integrated the proposed approach in a large RISC-V core, and we proved its effectiveness in detecting several versions of the Spectre, Orchestration, Rowhammer, and Flush + Reload attacks. In its best configuration, the proposed approach has been able to detect 100% of the attacks, with no false alarms and introducing about 10% area overhead, about 4% power increase, and without working frequency reduction

Modern field-programmable gate arrays (FPGAs) provide a vast amount of logic resources that can be used to implement complex systems while providing the flexibility to modify the design once deployed. This makes them attractive for software-defined networks (SDNs) applications, and, in fact, most vendors provide the building blocks needed for those applications, which include basic packet classification functions such as exact match, longest prefix match, and match with wildcards. Those are needed for different functions such as routing, security filtering, monitoring or quality of service. The match with wildcards can be done using ternary content addressable memories (TCAMs). TCAMs can be implemented as independent standalone devices or as Internet Protocol (IP) blocks that are used inside networking application-specific integrated circuits (ASICs) such as switching ICs. In both cases, the cells of a TCAM are more complex than that of a normal memory and also than that of a binary content addressable memory (CAMs). This is due to the more complex matching that they need to implement. As FPGAs are used in many different applications, it does not make sense to include TCAM blocks inside them as they would be used only in a small fraction of the systems. Therefore, TCAMs are emulated using the logic resources available inside the FPGA. In recent years, a number of schemes to emulate TCAMs on FPGAs have been proposed, some of them based on the use of the logic resources and others on the use of the embedded memory blocks available on the FPGA. In this brief, a technique to efficiently emulate TCAMs on Xilinx FPGAs is presented. The proposed scheme is based on the use of lookup tables (LUTs) and partial reconfiguration to achieve a more effective use of the FPGA resources while supporting the addition and removal of rules. The proposed scheme has been compared to existing implementations and the results show that it can achieve significant savings in resource usage. In addition, it enables the use of all the LUTs in the device for TCAM implementation, something that is not supported by existing approaches that use LUTRAMs.

Bloom filters are used to perform approximate membership checking in a wide range of applications in both computing and networking, but the recently introduced cuckoo filter is also gaining popularity. Therefore, it is of interest to compare both filters and provide insights into their features so that designers can make an informed decision when implementing approximate membership checking in a given application. This article first compares Bloom and cuckoo filters focusing on a packet classification application. The analysis identifies a shortcoming of cuckoo filters in terms of false positive rate when they do not operate close to full occupancy. Based on that observation, this article also proposes the use of a configurable bucket to improve the scaling of the false positive rate of the cuckoo filter with occupancy. Pedro Reviriego and David Larrabeiti would like to acknowledge the support of the ACHILLES project PID2019-104207RB-I00 and the Go2Edge network RED2018-102585-T funded by the Spanish Ministry of Science and Innovation and of the Madrid Community research project TAPIRCM grant no. P2018/TCS-4496. David Larrabeiti acknowledges the support of EU project PASSION, Grant Agreement 780326. Salvatore Pontarelli has been partly funded by the EU commission in the context of the 5G-PICTURE project, Grant Agreement 762057.

In many applications, there is a need to estimate the frequency of elements. For example, in networking to know the number of packets of each flow. This poses a challenge as the number of flows and packets per second can be very large and therefore an exact count would require a large amount of fast memory. In those cases, an alternative is to use data structures, commonly referred to as sketches, that provide an estimate of the frequency of elements using a much smaller amount of memory. For example, the Count Min Sketch (CMS) hashes each element to a few counters and returns as estimate the minimum value among them. The CMS in general overestimates the frequency of an element as other elements may also map to the same counters and increment them. In this letter, fingerprint counting, a scheme to reduce the counter overestimation is presented and evaluated. The main idea is to add a fingerprint to the counters and use it to check if consecutive increments to a counter belong to the same element. When they do not, the counters can be incremented by half a packet instead of a full packet thus reducing the overestimation. The evaluation results show that the proposed scheme is able to reduce the overestimation and improve the CMS accuracy. In more detail, the overestimation is reduced by more than 20% in many of the configurations tested reaching values over 50% in some cases. A scheme to encode the fingerprints in the counters that practically eliminates the additional memory required for the fingerprints is also presented. Therefore, the improvement in the accuracy is achieved with a negligible impact on the size of the memory needed to implement the CMS.

In a network it is interesting to know the different number of flows that traverse a switch or link or the number of connections coming from a specific sub-network. This is generally known as cardinality estimation or count distinct. The HyperLogLog (HLL) algorithm is widely used to estimate cardinality with a small memory footprint and simple per packet operations. However, with current line rates approaching a Terabit per second and switches handling many Terabits per second, even implementing HLL is challenging. This is mostly due to a bottleneck in accessing the memory as a random position has to be accessed for each packet. In this letter, we present and evaluate Fast Update HLL (FU-HLL), a scheme that eliminates the need to access the memory for most packets. Results show that FU-HLL can indeed significantly reduce the number of memory accesses when the cardinality is much larger than the number of registers used in HLL as it is commonly the case in practical settings.

The increasing performance requirements of modern applications place a significant burden on software-based packet processing. Most of today's software input/output accelerations achieve high performance at the expense of reserving CPU resources dedicated to continuously poll the Network Interface Card. This is specifically the case with DPDK (Data Plane Development Kit), probably the most widely used framework for software-based packet processing today. The approach presented in this paper, descriptively called Metronome, has the dual goals of providing CPU utilization proportional to the load, and allowing flexible sharing of CPU resources between I/O tasks and applications. Metronome replaces DPDK's continuous polling with an intermittent sleep&wake mode, and revolves around a new multi-threaded operation, which improves service continuity. Since the proposed operation trades CPU usage with buffering delay, we propose an analytical model devised to dynamically adapt the sleep&wake parameters to the actual traffic load, meanwhile providing a target average latency. Our experimental results show a significant reduction of the CPU cycles, improvements in power usage, and robustness to CPU sharing even when challenged with CPU-intensive applications.

In modern switches, a packet can go through a number of processing steps to determine, for example, if the packet has to be discarded due to security policies, if it needs to be marked for quality of service or to determine the next hop for the packet. Most of those steps can be modeled as a matching of some of the packet fields with a set of rules that are stored in the switch. This has been generalized with the adoption of Software Defined Networks, using for example, the Openflow protocol, on which the processing steps are programmable as table matching operations and defined dynamically by a controller. Implementing this flexible packet matching in a switch is challenging, as we need to support multiple matching tables, each having different key size, and the size of the tables should also be programmable. The main options to support multiple tables are to use different memories for each table or to have several tables share the same memories. In the first approach, each table would have to match the size and width of the memories to achieve an efficient memory usage. This is a severe limitation when flexible table size and entry width need to be supported. In the second approach, all the tables can dynamically share the memories, providing better flexibility. The problem is that the width of the memories needs to be dimensioned to support the largest entry size. This leads to significant memory waste for smaller entries. Hash based techniques like cuckoo hashing can be used to efficiently implement exact matching using standard SRAM memories, and are widely used in modern switches. However, current implementations only support entries of one size. This article presents the Single Double cuckoo hash, which can support elements of two sizes. Its main benefit is to improve memory utilization when multiple tables with entries of different sizes share the same memories. This is achieved at the cost of a small increase in circuit complexity.

Fault-tolerant systems are usually implemented with triple modular redundancy (TMR)-based protection techniques which has a huge area and power overhead. Previous works have shown that this overhead can be improved by using reduced precision redundancy (RPR)-based approaches for intrinsically precision-tolerant applications like image and video processing. The error detection and steering logic required in the RPR schemes utilize subtraction and comparisons which are more complex hardware operations than TMR voting. This overhead is affordable for complex hardware structures, for example, finite impulse response filters, but for simple structures like adders, it can be significant. In this letter, it is shown that combining the traditional TMR voting with the RPR brings up considerable savings in area and power budget when applied to very-large-scale integration adder circuits.

Ternary content addressable memories (TCAMs) are widely used in network devices to implement packet classification. They are used, for example, for packet forwarding, for security, and to implement software-defined networks (SDNs). TCAMs are commonly implemented as standalone devices or as an intellectual property block that is integrated on networking application-specific integrated circuits. On the other hand, field-programmable gate arrays (FPGAs) do not include TCAM blocks. However, the flexibility of FPGAs makes them attractive for SDN implementations, and most FPGA vendors provide development kits for SDN. Those need to support TCAM functionality and, therefore, there is a need to emulate TCAMs using the logic blocks available in the FPGA. In recent years, a number of schemes to emulate TCAMs on FPGAs have been proposed. Some of them take advantage of the large number of memory blocks available inside modern FPGAs to use them to implement TCAMs. A problem when using memories is that they can be affected by soft errors that corrupt the stored bits. The memories can be protected with a parity check to detect errors or with an error correction code to correct them, but this requires additional memory bits per word. In this brief, the protection of the memories used to emulate TCAMs is considered. In particular, it is shown that by exploiting the fact that only a subset of the possible memory contents are valid, most single-bit errors can be corrected when the memories are protected with a parity bit.

XTRA (XFSM for Transport) aims at providing a first attempt towards a “ code-once-port-everywhere ” platform-agnostic programming abstraction tailored to the deployment of transport layer functions. XTRA’s programming abstraction not only fits SW platforms, but is specifically designed to harness, with no re-coding effort, the offloading opportunities offered by CPU-less HW boards or smart NICs. We demonstrate the viability of XTRA with three completely different implementations of the underlying execution engine (HW proof-of-concept on a NetFPGA board, User-space SW over Linux’ Open Data Plane, and NS3 emulator). Flexibility is shown via a number of example applications, ranging from a variety of congestion control algorithms, to a middlebox-type TCP proxy functionality, up to a customized “Timer-Based” (TB) TCP which leverages the native reliance of XTRA on timers, so as to produce a loss recovery operation which, despite being formalized only via a handful of code lines, performs almost comparable with the highly optimized Linux and FreeBSD implementations.

Packet classification is an important part of many networking devices, such as routers and firewalls. Software-defined networking (SDN) heavily relies on online packet classification which must efficiently process two different streams: incoming packets to classify and rules to update. This rules out many offline packet classification algorithms that do not support fast updates. We propose a novel online classification algorithm, TupleMerge (TM), derived from tuple space search (TSS), the packet classifier used by Open vSwitch (OVS). TM improves upon TSS by combining hash tables which contain rules with similar characteristics. This greatly reduces classification time preserving similar performance in updates. We validate the effectiveness of TM using both simulation and deployment in a full-fledged software router, specifically within the vector packet processor (VPP). In our simulation results, which focus solely on the efficiency of the classification algorithm, we demonstrate that TM outperforms all other state of the art methods, including TSS, PartitionSort (PS), and SAX-PAC. For example, TM is 34% faster at classifying packets and 30% faster at updating rules than PS. We then experimentally evaluate TM deployed within the VPP framework comparing TM against linear search and TSS, and also against TSS within the OVS framework. This validation of deployed implementations is important as SDN frameworks have several optimizations such as caches that may minimize the influence of a classification algorithm. Our experimental results clearly validate the effectiveness of TM. VPP TM classifies packets nearly two orders of magnitude faster than VPP TSS and at least one order of magnitude faster than OVS TSS.

Cuckoo filters (CFs) are an alternative to Bloom filters (BFs) that supports deletions and can often be configured to have a lower false positive rate. A drawback of cuckoo filters is that the insertion process is complex and requires a large number of memory accesses when the filter operates at high occupancy. Therefore, insertion complexity may limit the applicability of cuckoo filters in many networking applications that require fast updates of the filter contents. In this letter, the cuckoo filter is extended to integrate a Bloom filter that is used to improve the performance of insertions. The proposed CFBF does not require additional memory accesses for lookup operations and preserves the support for deletion of the original cuckoo filter. The CFBF targets hardware implementations where the Bloom filter can be checked with negligible cost and where the memory width can also be adjusted to the bucket size. The evaluation results show that it can be used to reduce worst case insertion time by a factor of ten and achieve an average insertion time similar to that of a lookup. The CFBF can support bursts of hundreds of insertions for large filters and moderate false positive rates. Therefore, it can enable the use of hardware implemented cuckoo filters in applications that need to support bursts of insertions or to provide a low worst case insertion time.

In the last decade, a number of frameworks started to appear that implement, directly in userspace with kernel-bypass mode, high-speed software data plane functionalities on commodity hardware. Vector Packet Processor (VPP) is one of such frameworks, representing an interesting point in the design space in that it offers, in userspace networking, the flexibility of a modular router (Click and variants), with the benefits provided by techniques such as batch processing that have become commonplace in high-speed networking stacks (such as netmap or DPDK). Similarly to Click, VPP lets users arrange functions as a processing graph, providing a full-blown stack of network functions. However, unlike Click, where the whole tree is traversed for each packet, in VPP each traversed node processes all packets in the batch (called vector) before moving to the next node. This design choice enables several code optimizations that greatly improve the achievable processing throughput. This article introduces the main VPP concepts and architecture, and experimentally evaluates the impact of design choices (such as batch packet processing) on performance.

[EN] Static random access memories (SRAMs) are key in electronic systems. They are used not only as standalone devices, but also embedded in application specific integrated circuits. One key challenge for memories is their susceptibility to radiation-induced soft errors that change the value of memory cells. Error correction codes (ECCs) are commonly used to ensure correct data despite soft errors effects in semiconductor memories. Single error correction/double error detection (SEC-DED) codes have been traditionally the preferred choice for data protection in SRAMs. During the last decade, the percentage of errors that affect more than one memory cell has increased substantially, mainly due to multiple cell upsets (MCUs) caused by radiation. The bits affected by these errors are physically close. To mitigate their effects, ECCs that correct single errors and double adjacent errors have been proposed. These codes, known as single error correction/double adjacent error correction (SEC-DAEC), require the same number of parity bits as traditional SEC-DED codes and a moderate increase in the decoder complexity. However, MCUs are not limited to double adjacent errors, because they affect more bits as technology scales. In this brief, new codes that can correct triple adjacent errors and 3-bit burst errors are presented. They have been implemented using a 45-nm library and compared with previous proposals, showing that our codes have better error protection with a moderate overhead and low redundancy., This work was supported in part by the Universitat Politecnica de Valencia, Valencia, Spain, through the DesTT Research Project under Grant SP20120806; in part by the Spanish Ministry of Science and Education under Project AYA-2009-13300-C03; in part by the Arenes Research Project under Grant TIN2012-38308-C02-01; and in part by the Research Project entitled Manufacturable and Dependable Multicore Architectures at Nanoscale within the framework of COST ICT Action under Grant 1103.

Recent trends in emerging nonvolatile memory systems necessitate efficient read/write (R/W) schemes. Efficient solutions with zero sneak path current, nondestructive R/W operations, minimum area and low power are some of the key requirements. Toward this end, we propose a novel crossbar memory scheme using a configuration row of cells for assisting R/W operations. The proposed write scheme minimizes the overall power consumption compared to the previously proposed write schemes and reduces the state drift problem. We also propose two read schemes, namely, assisted-restoring and self-resetting read. In assisted-restoring scheme, we use the configuration cells which are used in the write scheme, whereas we implement additional circuitry for self-reset which addresses the problem of destructive read. Moreover, by formulating an analytical model of R/W operation, we compare the various schemes. The overhead for the proposed assisted-restoring write/read scheme is an extra redundant row for the given crossbar array. For a typical array size of $200\times 200$ the area overhead is about $0.5\%$ , however, there is a 4X improvement in power consumption compared to the recently proposed write schemes. Quantitative analysis of the proposed scheme is analyzed by using simulation and analytical models.

Single error correction-double error detection- double adjacent error correction (SEC-DED-DAEC) codes have been proposed to protect SRAM devices from multiple cell upsets (MCUs). The correction of double adjacent errors ensures that the most common types of MCUs are corrected. At the same time, SEC-DED-DAEC codes require the same number of parity check bits as traditional SEC-DED codes. The main overhead associated with SEC-DED-DAEC codes is the increase in decoding complexity that can impact access time and circuit power and area. In this paper, a method to design SEC-DED-DAEC codes with optimized decoding is presented and evaluated. The proposed scheme starts by setting some constraints on the parity check matrix of the codes. Those constraints are then used to simplify the decoding. The proposed scheme has been implemented and evaluated for different word-lengths. The results show that, for data words of 32 bits, the scheme can be implemented with the same number of parity check bits as SEC-DED codes. For 16 and 64 bits words, an additional parity check bit is required, making the scheme less attractive. With the proposed method, the decoders can be optimized for area or speed. Both implementations are evaluated and compared with existing SEC-DED-DAEC decoders. The results show that the proposed decoders reduce significantly the circuit area, power, and delay. Index Terms—SEC-DAEC codes, Multiple Cell Upsets (MCUs), error correction codes, SRAM memories.

We introduce a new hardware/software platform for testing SRAM-based FPGAs under heavy-ion and neutron beams, capable of tracing the bit-flips in the configuration memory back to the physical resources affected in the FPGA. The validation was performed using, for the first time, the neutron source at the RALILSIS facility. The ISlS beam features a 1/E spectrum, which is similar to the terrestrial one with an acceleration between 107 and 10 8 in the energy range 10-100 MeV. The results gathered on Xilinx SRAM-based FPGAs are discussed in terms of cross section and circuit-level modifications. © 2007 IEEE.

Error correction codes (ECCs) are commonly used to protect memories against errors. Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for memory protection due to their modularity and the simplicity of the decoding algorithm that enables low delay implementations. An important issue is that when ECCs are used, the encoder and decoder circuits can also suffer errors. In this brief, a concurrent error detection technique for OLS codes encoders and syndrome computation is proposed and evaluated. The proposed method uses the properties of OLS codes to efficiently implement a parity prediction scheme that detects all errors that affect a single circuit node.

This brief presents a technique to efficiently correct single soft errors in serial shift registers. The proposed scheme uses two copies of the shift register. To achieve error correction, data are convolutionally encoded at the input of one of the copies and are decoded at its output. This processing ensures that in that copy, any error affecting a single bit will corrupt its output for multiple cycles. On the other hand, a single-bit error in the original copy will corrupt its output only for one cycle. Therefore, the error patterns can be used to identify the copy that has suffered the error and, consequently, to correct the error. The proposed technique has been implemented in a Hardware Description Language and implemented in a 45-nm library. A fault injection tool has been used to evaluate the effectiveness of the proposed scheme, showing that it can correct all single soft errors. The cost of the proposed approach in terms of circuit area has been compared with a traditional triple-modular redundancy implementation. The results show significant cost reductions, which approach a factor of 33% for large shift registers.

Soft errors that corrupt the value of bits stored in registers or memories are a major issue for modern electronic systems. To ensure that they do not cause failures, error detection and correction codes are commonly used to protect memories. When memories are used for a specific application, sometimes it is possible to optimize the protection based on the knowledge of the application. One example is the memories used in network devices for packet processing. In particular, the protection of approximate membership check structures such as Bloom filters has been recently studied showing that it is possible to optimize the protection. Cuckoo filters are an alternative to Bloom filters for approximate membership check that has been recently proposed. Cuckoo filters are interesting as they are competitive in terms of memory usage for low false positive rates and also support the removal of elements. In this paper, the protection of Cuckoo filters against soft errors is studied showing that it can be enhanced by exploiting its structure and using the knowledge of the effects on an error in a Cuckoo filter.

Error correction codes (ECCs) have been used for decades to protect memories from soft errors. Single error correction (SEC) codes that can correct 1-bit error per word are a common option for memory protection. In some cases, SEC codes are extended to also provide double error detection and are known as SEC-DED codes. As technology scales, soft errors on registers also became a concern and, therefore, SEC codes are used to protect registers. The use of an ECC impacts the circuit design in terms of both delay and area. Traditional SEC or SEC-DED codes developed for memories have focused on minimizing the number of redundant bits added by the code. This is important in a memory as those bits are added to each word in the memory. However, for registers used in circuits, minimizing the delay or area introduced by the ECC can be more important. In this paper, a method to construct low delay SEC or SEC-DED codes that correct errors only on the data bits is proposed. The method is evaluated for several data block sizes, showing that the new codes offer significant delay reductions when compared with traditional SEC or SEC-DED codes. The results for the area of the encoder and decoder also show substantial savings compared to existing codes.

Cache memories are very relevant components in modern processors, and therefore, their protection against soft errors is important to ensure reliability. One important element in caches is the tag fields, which are critical to keep data integrity and achieve a high hit ratio. To protect them against soft errors, a parity bit or a single error correction (SEC) code is commonly used. In that case, on each cache access, the parity bit is checked or the SEC code decoded on each cache way to detect and correct errors. In this paper, FastTag, a novel approach to protect cache tags is presented and evaluated. The proposed scheme computes the parity or SEC bits on the incoming address and compares the result with the tag and parity bits stored in each cache way. This avoids parity recomputation or SEC decoding, thus reducing the circuit complexity. This is corroborated by the evaluation results that show how FastTag requires an area, delay, and power overhead much lower than the conventional techniques that are currently used.

Many techniques have been proposed in the technical literature for repairing FPGAs when affected by permanent faults. Almost all of these works exploit the dynamic reconfiguration capabilities of an FPGA where a subset of the available resources is used as spares for replacing the faulty ones. The choice of the best reconfiguration technique depends on both the required reliability and on the architecture of the chosen FPGA . This paper presents a survey of these techniques and explains how the architectural organization of the FPGA affects the choice of a reconfiguration strategy. Subsequently, a framework is proposed for these techniques by which a fair comparison among them can be assessed and evaluated with respect to reliability. A reliability evaluation is provided for different repair strategies. To provide a comparison between these techniques FPGAs of different size are taken into account. Also the relationship between the area overhead and the overall reliability has been investigated. Considerations about time to repair and feasibility of these techniques are provided. The ultimate goal of this paper is therefore to present a state-of-the-art repair techniques as applicable to FPGA and to establish their performance for reliability.

Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2m). These properties are related to the parity of the binary representation of the elements of the Galois field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented.

Hash tables are one of the most commonly used data structures in computing applications. They are used for example to organize a data set such that searches can be performed efficiently. The data stored in a hash table is commonly stored in memory and can suffer errors. To ensure that data stored in a memory is not corrupted when it suffers errors, Error Correction Codes (ECCs) are commonly used. In this research note a scheme to efficiently implement ECCs for the entries stored in hash tables is presented. The main idea is to use an ECC as the hash function that is used to construct the table. This eliminates the need to store the parity bits for the entries in the memory as they are implicit in the hash table construction thus reducing the implementation cost.

In this paper, an innovative fault tolerant solid state mass memory (FTSSMM) architecture is described. Solid state mass memories (SSMMs) are particularly suitable for space applications and more in general for harsh environments such us, for example, nuclear accelerators or avionics. The presented FTSSMM design has been entirely based on commercial off the shelf (COTS) components. In fact, cost competitive and very high performance SSMMs cannot be easily implemented by using space qualified components, due the technological gap and very high cost characterizing these components. In order to match the severe reliability requirements of space applications a COTS-based apparatus must be designed by using suitable system level methodologies (Kluth, 1996 and Fichna, 1998). In the proposed architecture, error-correcting codes are used to strengthen the commercial dynamic random access memory (DRAM) chips, while the system controller has been designed by applying suitable fault tolerant design techniques. Different from other proposed solutions, our architecture fully exploits the reconfiguration capabilities of Reed-Solomon (RS) codes, discriminates between permanent and transient faults reducing the use of spare elements, and provides dynamic reconfiguration and graceful degradation capability, i.e., the FTSSMM performances are gracefully reduced in case of permanent faults, maintaining part of the system functionality. The paper shows the FTSSMM design methodology, the architecture, the reliability analysis, some simulation results, and a description of its implementation based on fast prototyping techniques.

Radiation-induced soft errors are a major reliability concern for memories. To ensure that memory contents are not corrupted, single error correction double error detection (SEC-DED) codes are commonly used, however, in advanced technology nodes, soft errors frequently affect more than one memory bit. Since SEC-DED codes cannot correct multiple errors, they are often combined with interleaving. Interleaving, however, impacts memory design and performance and cannot always be used in small memories. This limitation has spurred interest in codes that can correct adjacent bit errors. In particular, several SEC-DED double adjacent error correction (SEC-DED-DAEC) codes have recently been proposed. Implementing DAEC has a cost as it impacts the decoder complexity and delay. Another issue is that most of the new SEC-DED-DAEC codes miscorrect some double nonadjacent bit errors. In this brief, a new class of SEC-DED-DAEC codes is derived from orthogonal latin squares codes. The new codes significantly reduce the decoding complexity and delay. In addition, the codes do not miscorrect any double nonadjacent bit errors. The main disadvantage of the new codes is that they require a larger number of parity check bits. Therefore, they can be useful when decoding delay or complexity is critical or when miscorrection of double nonadjacent bit errors is not acceptable. The proposed codes have been implemented in Hardware Description Language and compared with some of the existing SEC-DED-DAEC codes. The results confirm the reduction in decoder delay.

International audience; This article presented a survey of dependability issues faced by multi-core architectures at nanoscale technology nodes. Existing solutions against these challenges were also discussed, describing their scope of application, from technology level methodologies, to design approaches to the metrics required to evaluate the overall dependability of a system. In the future, the constant reduction of the feature size of the devices will exacerbate the issues related to aging and soft errors. This will create further challenges and at design level, an integrated design approach that will cope with the occurrence of faults at any time of their occurrence i.e., at manufacturing (thus increasing yield) and in the field (thus increasing reliability) will become more and more important to obtain economically viable and dependable systems. Dependability assessment will also need an integrated approach for cross-layer, pre- and post-silicon techniques for “just right”dependability assessment in order to avoid “overdesign”for dependability using classic guard-banding methodologies.

Complementary resistive switching (CRS) memristor is an emerging nonvolatile memory device that features low-sneak path current compared to traditional memristors. Despite its advantages, threshold voltage and doping interface drift speed variations over time are major concerns for CRS memory devices. In this paper, we will demonstrate that these variations can significantly reduce the CRS lifetime reliability in terms of number of memory operations that can be performed. Based on such demonstrations, comprehensive theoretical and empirical studies are carried out using H-Spice based simulations to investigate the impact of biasing and threshold voltages on CRS lifetime reliability. Underpinning these studies, a novel CRS lifetime relationship is proposed and extensively validated through further simulations.

Bloom filters (BFs) provide a fast and efficient way to check whether a given element belongs to a set. The BFs are used in numerous applications, for example, in communications and networking. There is also ongoing research to extend and enhance BFs and to use them in new scenarios. Reliability is becoming a challenge for advanced electronic circuits as the number of errors due to manufacturing variations, radiation, and reduced noise margins increase as technology scales. In this brief, it is shown that BFs can be used to detect and correct errors in their associated data set. This allows a synergetic reuse of existing BFs to also detect and correct errors. This is illustrated through an example of a counting BF used for IP traffic classification. The results show that the proposed scheme can effectively correct single errors in the associated set. The proposed scheme can be of interest in practical designs to effectively mitigate errors with a reduced overhead in terms of circuit area and power.

This paper presents a novel high-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors other than double-adjacent errors. Its operation is based on extending an existing parallel BCH decoder that can only correct single-bit errors and serially corrects double-adjacent errors at low speed. The proposed decoder is constructed by a novel design and is suitable for nanoscale memory systems, in which multiple-bit errors occur at a probability comparable to single-bit errors and double-adjacent errors occur at a higher probability (nearly two orders of magnitude) than other multiple-bit errors. Extensive simulation results are reported. Compared with the existing scheme, the area and delay time of the proposed decoder are on average 11% and 6% higher, but its power consumption is reduced by 9% on average. This paper also shows that the area, delay, and power overheads incurred by the proposed scheme are significantly lower than traditional fully parallelized BCH decoders capable of correcting any double-bit errors in parallel.

The papers in this special issue focus on defect and fault tolerance in VLSI and nanotechnology systems. With the increasing demand for ever smaller, portable, energy-efficient and high-performance electronic systems, scaling of CMOS technology continues. As CMOS scaling approaches physical limits, continued innovation in materials, manufacturing processes, device structures and design paradigms have been necessary. High-k oxide and metal-gate stack were introduced to address oxide leakage; thin body undoped channels, and multiple-gate structures were introduced to mitigate subthreshold leakage; restricted design rules were introduced to improve layout efficiency; yet CMOS technology continues to be challenged in the areas of device aging and reliability. While CMOS is expected to be the dominant semiconductor technology for the foreseeable future, for reasons that are both technological and financial, alternatives to CMOS technology are attracting attention from the researchers.

The last few years have seen the development and fabrication of nanoscale circuits at high density and low power. Following a single-event upset (SEU), so-called soft errors due to internal and externally induced phenomena (such as α-particles and cosmic rays in adverse environments) have been reported during system operation; this is especially deleterious for storage elements such as flip-flops. To reduce the impact of a soft error on flip-flops, hardening techniques have been utilized. This paper proposes two new slave latches for improving the SEU tolerance of a flip-flop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. When used in a flip-flop, the first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16% (9%) power consumption overhead at 32-nm feature size, as compared with the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple-node upset.

Energy efficiency has become an important design goal for networking equipment. Traditionally routers and switches have been designed to minimize peak power consumption but they operate most of the time with settings and traffic that is far from that peak. Therefore, many elements and functions of networking equipment are being redesigned to improve energy efficiency. A common functionality in networking is flow identification that is needed in many applications. Flow identification can be implemented with Content Addressable Memories (CAMs) or alternatively with several data structures. Among those, one efficient option is Cuckoo hashing that enables fast searches and high memory utilization at the cost of complicating the insertion procedure. In this letter, first the energy efficiency of exact matching using Cuckoo hashing is analyzed and then a technique is presented to improve the energy efficiency of Cuckoo hashing. The proposed scheme is evaluated using a traffic monitoring application and compared with the traditional Cuckoo hashing. The results show that significant energy savings can be obtained by using the proposed technique.

Error correction codes (ECCs) are commonly used to protect memories from errors. As multibit errors become more frequent, single error correction codes are not enough and more advanced ECCs are needed. The use of advanced ECCs in memories is, however, limited by their decoding complexity. In this context, one-step majority logic decodable (OS-MLD) codes are an interesting option as the decoding is simple and can be implemented with low delay. Orthogonal Latin squares (OLS) codes are OS-MLD and have been recently considered to protect caches and memories. The main advantage of OLS codes is that they provide a wide range of choices for the block size and the error correction capabilities. In this brief, a method to extend OLS codes is presented. The proposed method enables the extension of the data block size that can be protected with a given number of parity bits thus reducing the overhead. The extended codes are also OS-MLD and have a similar decoding complexity to that of the original OLS codes. The proposed codes have been implemented to evaluate the circuit area and delay needed for different block sizes.

The fast evolving nature of modern cyber threats and network monitoring needs calls for new, "software-defined", approaches to simplify and quicken programming and deployment of online (stream-based) traffic analysis functions. StreaMon is a carefully designed data-plane abstraction devised to scalably decouple the "programming logic" of a traffic analysis application (tracked states, features, anomaly conditions, etc.) from elementary primitives (counting and metering, matching, events generation, etc), efficiently pre-implemented in the probes, and used as common instruction set for supporting the desired logic. Multi-stage multi-step real-time tracking and detection algorithms are supported via the ability to deploy custom states, relevant state transitions, and associated monitoring actions and triggering conditions. Such a separation entails platform-independent, portable, online traffic analysis tasks written in a high level language, without requiring developers to access the monitoring device internals and program their custom monitoring logic via low level compiled languages (e.g., C, assembly, VHDL). We validate our design by developing a prototype and a set of simple (but functionally demanding) use-case applications and by testing them over real traffic traces.

Error correction codes (ECCs) are commonly used to protect memory devices from errors. The most commonly used codes are a simple parity bit and single-error-correction (SEC) codes. A parity bit enables single-bit error detection, whereas a SEC code can correct one-bit errors. A SEC code requires more additional bits per word and also more complex decoding that impacts delay. A tradeoff between both schemes is the use of a product code based on a combination of two parity bits. This approach reduces the memory overhead at the expense of a more complex access procedure. In this letter, an alternative scheme based on the use of parity sharing is proposed and evaluated. The results show that the new approach significantly reduces the memory overhead and is also capable of correcting single-bit errors.

Reliability is a major concern for memories. To ensure that errors do not affect the data stored in a memory, error correction codes (ECCs) are widely used in memories. ECCs introduce an overhead as some bits are added to each word to detect and correct errors. This increases the cost of the memory. Content addressable memories (CAMs) are a special type of memories in which the input is compared with the data stored, and if a match is found, the output is the address of that word. CAMs are used in many computing and networking applications. In this brief, the specific features of CAMs are used to reduce the cost of implementing ECCs. More precisely, the proposed technique eliminates the need to store the ECC bits for each word in the memory. This is done by embedding those bits into the address of the key. The main potential issue of the new scheme is that it restricts the addresses in which a new key can be stored. Therefore, it can occur that a new key cannot be added into the CAM when there are addresses that are not used. This issue is analyzed and evaluated showing that, for large CAMs, it would only occur when the CAM occupancy is close to 100%. Therefore, the proposed scheme can be used to effectively reduce the cost of implementing ECCs in CAMs.

In modern signal processing circuits, it is common to find several filters operating in parallel. In this letter, we propose an area efficient technique to detect and correct single errors occurring in pairs of parallel filters that have either the same input data or the same impulse response. The technique uses a primary implementation comprised of two independent filters and a redundant implementation that shares input data between both filters so as to detect and correct errors. Herein, the area cost of the proposed scheme is shown to be slightly more than double that of the unprotected filter, whereas the conventional Triple Modular Redundancy solution requires an area three times that of the unprotected filter. Spanish Ministry of Science and Education

Galois fields are widely used in cryptographic applications. The detection of an error caused by a fault in a cryptographic circuit is important to avoid undesirable behaviours of the system that could be used to reveal secret information. One of the methods used to avoid these behaviours is the concurrent error detection. Multiplication in finite field is one of the most important operations and is widely used in different cryptographic systems. The authors propose in this study an error-detection method for composite finite-field multipliers based on the use of Karatsuba formula. The Karatsuba formula can be used in GF((2n)2) field to decrease the hardware complexity of the finite-field multiplier. The authors propose a novel finite-field multiplier with concurrent error-detection capabilities based on the Karatsuba formula. How the error-detection capabilities of this multiplier are able to face a wide range of fault-based attacks is also shown.

This paper introduces an architecture for quantum-dot cellular automata circuits with the potential for high throughput and low power dissipation. The combination of regions with Bennett clocking and memory storage combines the low power advantage of reversible computing with the high throughput advantage of pipelining. Two case studies are initially presented to evaluate the proposed pipelined architecture in terms of throughput and power consumption due to information dissipation. A general model for assessing power consumption is also proposed. This paper shows that the advantages possible by using a Bennett clocking scheme also depend on circuit topology, thus also confirming the validity of the proposed analysis and model.

In this paper, different circuits of Quantum-dot Cellular Automata (QCA) are proposed for the so-called coplanar crossing. Coplanar crossing is one of the most interesting features of QCA because it allows for mono-layered interconnected circuits, whereas CMOS technology needs different levels of metalization. However, the characteristics of the coplanar crossing make it prone to malfunction due to thermal noise or defects. The proposed circuits exploit the majority voting properties of QCA to allow a robust crossing of wires on the Cartesian plane. This is accomplished using enlarged lines and voting. A Bayesian Network (BN) based simulator is utilized for evaluation; results are provided to assess robustness in the presence of cell defects and thermal effects. The BN simulator provides fast and reliable computation of the signal polarization versus normalized temperature. Simulation of the wire crossing circuits at different operating temperatures is provided with respect to defects and a quantitative metric for performance under temperature variations is proposed and assessed.

The authors present a novel memory architecture for quantum-dot cellular automata (QCA). The proposed architecture combines the advantage of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory, hence its name is 'hybrid'. This hybrid architecture utilises a novel arrangement in the addressing circuitry of the QCA loop for implementing the memory-in-motion paradigm. An evaluation of latency and area is pursued. It is shown that while for a serial memory, latency is O(N )( whereN is the number of bits in a loop), a constant latency is accomplished in the hybrid memory. For area analysis, a novel characterisation that considers cells in the logic circuitry, interconnect in addition to the unused portion of the Cartesian plane (i.e. the whole geometric area encompassing the QCA layout), is proposed. This is referred to as the effective area. Different layouts of the hybrid memory are proposed to substantiate the reduction in effective area.

This paper addresses the design of storage systems for operation under critical environmental conditions. For these applications, these systems should have low latency time in access, high performance in throughput and high storage capabilities; therefore, they must be assembled using highly reliable components, while allowing flexibility in design. Commercial Off The Shelf (COTS) components have often been used. A COTS-based architecture is analyzed in this paper; the proposed architecture uses design-level techniques (such as error detection/correction codes and scrubbing) to make commercially available Dynamic Random Access Memory (DRAM) chips tolerant to faults. This paper provides a complete and novel analysis of engineering alternatives which arise in the design of a highly reliable memory system based on Reed Solomon coding. A comparative analysis of methods for permanent fault detection is provided; moreover using a Markovian characterization, different functional arrangements (based on code and scrubbing frequency) are investigated and evaluated.

Error correction codes are commonly used in memories to ensure that data are not corrupted. Single error correction double error detection (SEC-DED) codes are among the most widely used codes to protect memories. One common technique to implement SEC-DED codes is to construct a parity check matrix with odd-weight columns. This ensures that double errors have an even weight syndrome and therefore are not confused with single errors thus providing the DED feature. Recently, a technique that reduces the decoding complexity for odd-weight SEC-DED codes has been proposed. This technique can be used only for small data block sizes being the practical limit 32 bits. However, memories with 64 bits are commonly found in modern computing systems. Therefore, it would be advantageous to also reduce the decoding complexity for larger block sizes. A scheme to optimise the decoding of odd-weight SEC-DED codes with block sizes of 64 bits is presented and evaluated. The results show that the new scheme can provide significant reductions in the decoder circuitry area and delay.

This paper describes a novel architecture of fault tolerant solid state mass memory (SSMM) for satellite applications. Mass memories with low-latency time, high throughput, and storage capabilities cannot be easily implemented using space qualified components, due to the inevitable technological delay of these kind of components. For this reason, the choice of commercial off the shelf (COTS) components is mandatory for this application. Therefore, the design of an electronic system for space applications, based on commercial components, must match the reliability requirements using system level methodologies. In the proposed architecture, error-correcting codes are used to strengthen the commercial dynamic random access memory (DRAM) chips, while the system controller is developed by applying fault tolerant design solutions. The main features of the SSMM are the dynamic reconfiguration capability, and the high performances which can be gracefully reduced in case of permanent faults, maintaining part of the system functionality. The paper shows the system design methodology, the architecture, and the simulation results of the SSMM. The properties of the building blocks are described in detail both in their functionality and fault tolerant capabilities. A detailed analysis of the system reliability and data integrity is reported. The graceful degradation capability of our system allows different levels of acceptable performances, in terms of active I/O link interfaces and storage capability. The results also show that the overall reliability of the SSMM is almost the same using different RS coding schemes, allowing a dynamic reconfiguration of the coding to reduce the latency (shorter codewords), or to improve the data integrity (longer codewords). The use of a scrubbing technique can be useful if a high SEU rate is expected, or if the data must be stored for a long period in the SSMM. The reported simulations show the behavior of the SSMM in presence of permanent and transient faults. In fact, we show that the SCU is able to recover from transient faults. On the other hand, using a spare microcontroller also hard faults can be tolerated. The distributed file system confines the unrecoverable fault effects only in a single I/O Interface. In this way, the SSMM maintains its capability to store and read data. The proposed system allows obtaining SSMM characterized by high reliability and high speed due the intrinsic parallelism of the switching matrix.

Soft errors that affect flip-flops are a major issue in advanced electronic circuits. As technology scales, multiple bit errors become more likely. This limits the applicability of traditional protection techniques like triplication with voting or single error correction codes that can correct only one error. Multiple errors tend to affect adjacent bits, and therefore it is interesting to use error correction codes that can correct adjacent errors. The issue with these codes is that they require a large area and delay that limits their use to protect flip-flops in circuits. Presented are codes that can be implemented with low area and delay and can correct multiple adjacent errors.