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The aim of this study was to develop a flexible package technology using laser-assisted bonding (LAB) technology and an anisotropic solder paste (ASP) material ultimately to reduce the bonding temperature and enhance the flexibility and reliability of flexible devices. The heat transfer phenomena during the LAB process, mechanical deformation, and the flexibility of a flexible package were analyzed by experimental and numerical simulation methods. The flexible package was fabricated with a silicon chip and a polyimide (PI) substrate. When the laser beam was irradiated onto the flexible package, the temperatures of the solder increased very rapidly to 220 °C, high enough to melt the ASP solder, within 2.4 s. After the completion of irradiation, the temperature of the flexible package decreased quickly. It was found that the solder powder in ASP was completely melted and formed stable interconnections between the silicon chip and the copper pads, without thermal damage to the PI substrate. After the LAB process, the flexible package showed warpage of 80 μm, which was very small compared to the size of the flexible package. The stress of each component in the flexible package generated during the LAB process was also found to be very low. The flexible device was bent up to 7 mm without failure, and the flexibility can be improved further by reducing the thickness of the silicon chip. The bonding strength and environmental reliability tests also showed the excellent mechanical endurance of the flexible package.

A highly reliable conductive adhesive obtained by transient liquid‐phase sintering (TLPS) technologies is studied for use in high‐power device packaging. TLPS involves the low‐temperature reaction of a low‐melting metal or alloy with a high‐melting metal or alloy to form a reacted metal matrix. For a TLPS material (consisting of Ag‐coated Cu, a Sn96.5‐Ag3.0‐Cu0.5 solder, and a volatile fluxing resin) used herein, the melting temperature of the metal matrix exceeds the bonding temperature. After bonding of the TLPS material, a unique melting peak of TLPS is observed at 356 °C, consistent with the transient behavior of Ag3Sn + Cu6Sn5 → liquid + Cu3Sn reported by the National Institute of Standards and Technology. The TLPS material shows superior thermal conductivity as compared with other commercially available Ag pastes under the same specimen preparation conditions. In conclusion, the TLPS material can be a promising candidate for a highly reliable conductive adhesive in power device packaging because remelting of the SAC305 solder, which is widely used in conventional power modules, is not observed.

The effects of the material properties of the underfill layer on thermal stress and deformation in 3D through silicon via (TSV) integration packages were evaluated through numerical analysis. Sample TSV packages with underfill composed of different silica volume ratios were fabricated. The sample packages were used to measure thermal deformation using a Moire interferometer. Also, a cross-section from these samples was used for 2D finite element modeling and numerical analysis to obtain its thermal deformation. The experimental and numerical results were compared to confirm the suitability of the numerical technique in this research. A four-chip-stacked TSV integration package, which includes underfill layers of four different silica volume ratios, was proposed and designed. The diagonal part of the TSV integration packages were three dimensionally modeled and adopted for numerical analysis. Among the underfill with different silica volume ratios in the designed packages, a silica volume ratio of around 20% shows the best performance for a reliable flip chip bonding process, effectively minimizing thermal stress and deformation in the package.

Integration technologies involving flexible substrates are receiving significant attention owing the appearance of new products regarding wearable and Internet of Things technologies. There has been a continuous demand from the industry for a reliable bonding method applicable to a low-temperature process and flexible substrates. Up to now, however, an anisotropic conductive film (ACF) has been predominantly used in applications involving flexible substrates; we therefore suggest low-temperature lead-free soldering and bonding processes as a possible alternative for flex-on-flex applications. Test vehicles were designed on polyimide flexible substrates (FPCBs) to measure the contact resistances. Solder bumping was carried out using a solder-on-pad process with Solder Bump Maker based on Sn58Bi for low-temperature applications. In addition, thermocompression bonding of FPCBs was successfully demonstrated within the temperature of 150 °C using a newly developed fluxing underfill material with fluxing and curing capabilities at low temperature. The same FPCBs were bonded using commercially available ACFs in order to compare the joint properties with those of a joint formed using solder and an underfill. Both of the interconnections formed with Sn58Bi and ACF were examined through a contact resistance measurement, an 85 °C and 85% reliability test, and an SEM cross-sectional analysis.

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are , , and , respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than . InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than . A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip-chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at .

Popular solder-bumping mechanisms such as electroplating and stencil printing suffer from either high process costs or technical limitations. A low-cost solder-on-pad (SoP) process has been developed to meet the requirements of fine-pitch solder bumping. This paper focuses on the characterization and estimation of the SoP process. To form a solder bump without soldering defects, optimum process conditions should be carefully designed. A model to estimate the bump volume and predict the bump height is suggested. By optimizing the composition of solder paste material called solder-bump-maker, and by adjusting the process conditions, Sn-Ag-Cu solder bumps with different heights are obtained. The experiments and analysis to understand the impact of parameters were based on test vehicles with 80 μm pitch size. Then, the measured heights of solder bumps are compared with the model to see how they fit the estimation. Finally, a similar process has been conducted to test vehicles with pitch sizes of 150 and 40 μm, to confirm the scalability of the SoP process in different pitch sizes.

For the fine-pitch application of flip-chip bonding with semiconductor packaging, fluxing and hybrid underfills were developed. A micro-encapsulated catalyst was adopted to control the chemical reaction at room and processing temperatures. From the experiments with a differential scanning calorimetry and viscometer, the chemical reaction and viscosity changes were quantitatively characterized, and the optimum type and amount of micro-encapsulated catalyst were determined to obtain the best pot life from a commercial viewpoint. It is expected that fluxing and hybrid underfills will be applied to fine-pitch flip-chip bonding processes and be highly reliable.

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-μm pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-μm diameter and 60-μm pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

For the formation of solder bumps with a fine pitch of 130 μm on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of 220°C. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 μ m, 18.3 μm, and 12.0 μm, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is successfully formed.

Through silicon via (TSV)-based 3-D integrated circuit has introduced the solution to limitlessly growing demand on high system bandwidth, low power consumption, and small form factor of electronic devices. As the system design aims for higher performance, the physical dimensions of the channels are continuously decreasing. With TSV diameter of less than 10 $\mu \text{m}$ and pitch of several tens of micrometers, the I/O count has increased up to the order of tens of thousands for wide bandwidth data transmission. However, without highly precise fabrication process, such small structures are susceptible to a variety of defects. For the first time, in this paper, we propose a noninvasive defect analysis method for high-speed TSV channel. With designed and fabricated test vehicles, the proposed method is demonstrated with ${S}$ -parameter and time-domain reflectometry measurement results. In addition, we present equivalent circuit models of TSV daisy-chain structures, including the circuit components for open defect and short defect. With characterized dominant factors in each frequency range, $S_{11}$ is analyzed to distinguish and locate the defects by the amount of capacitance, resistance, and inductance that the signal experiences. ${S}$ -parameter measurement sufficiently allows high-frequency defect analysis of TSV channel without destroying the test sample. We experimentally verified the accuracy of the suggested model by comparing the ${S}$ -parameter results from circuit simulations and measurements. Finally, the model is modified to discuss the effects of open defect and short defect on the electrical characteristics of TSV channel.

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

Using high-speed through-silicon via (TSV) channels is a potential means of utilizing 3-D interconnections to realize considerable high-bandwidth throughput in vertically stacked and laterally distributed integrated circuits. However, although the TSV and a silicon interposer in a high-speed TSV channel lead to a significant decrease of the interconnect length, the received digital signal after transmission through a TSV channel is still degraded at a high data-rate due to the nonidealities of the channel. Therefore, an analysis of the signal integrity in a high-speed TSV channel is necessary. In this paper, a single-ended high-speed TSV channel is measured and analyzed in the frequency-domain and the time-domain. To measure the high-speed TSV channel, two types of test vehicles are fabricated, consisting of TSVs and interposers. With these test vehicles, the channel losses are measured in the frequency-domain up to 20 GHz, and eye-diagrams are measured in the time-domain at 1 Gb/s and 10 Gb/s. Based on these measurements, the channel loss, characteristic impedance, and reflection of the high-speed TSV channel are analyzed and compared to those of the channel in multichip module (MCM) package. Because of the losses from the silicon-substrate and the thin oxide-layer used in the TSVs, the overall loss of the high-speed TSV channel is higher than that of the MCM channel. In addition, the characteristic impedance of the high-speed TSV channel is frequency-dependent, whereas that of the MCM channel is frequency-independent. Moreover, in contrast to the MCM channel, the reflection is negligible in the high-speed TSV channel because the channel is too short and the losses are too high to be affected by the reflection. Finally, the design guidance of a high-speed TSV channel for wide bandwidth is determined based on the analysis of the measurements.

As an isotropic conductive adhesive, that is, a hybrid Cu paste composed of Cu powder, solder powder, and a fluxing resin system, has been quantitatively characterized. The mechanism of an electrical connection based on a novel concept of electrical conduction is experimentally characterized using an analysis of a differential scanning calorimeter and scanning electron microscope energydispersive X-ray spectroscopy. The oxide on the metal surface is sufficiently removed with an increase in temperature, and intermetallic compounds between the Cu and melted solder are simultaneously generated, leading to an electrical connection. The reliability of the hybrid Cu paste is experimentally identified and compared with existing Ag paste. As an example of a practical application, the hybrid Cu paste is used for LED packaging, and its electrical and thermal performances are compared with the commercialized Ag paste. In the present research, it is proved that, except the optical function, the electrical and thermal performances are similar to pre-existing Ag paste. The hybrid Cu paste could be used as an isotropic conductive adhesive due to its low production cost.

A novel bumping material, which is composed of a resin and Sn3Ag0.5Cu (SAC305) solder power, has been developed for the maskless solder-on-pad technology of the fine-pitch flip- chip bonding. The functions of the resin are carrying solder powder and deoxidizing the oxide layer on the solder power for the bumping on the pad on the substrate. At the same time, it was designed to have minimal chemical reactions within the resin so that the cleaning process after the bumping on the pad can be achieved. With this material, the solder bump array was successfully formed with pitch of 150 µm in one direction. 150 µm. The proposed technologies were solder jetting, controlled collapse chip connection new process (C4NP), electro-plating, micro-ball placement, super solder, and so on. Each technology has its own disadvantages, such as expensive equipment, low throughput, and environmental problems. In this letter, we propose a novel bumping material for SoP technology. The basic idea is similar to the solder bump maker (SBM), which is based on the rheological behavior of the solder in resin (3)-(5). However, the major component of the resin in the SBM was epoxy, the solder of which has a low- melting-point, making the SBM inapplicable to the SoP technology. To resolve those problems, we adopted the Sn3Ag0.5Cu (SAC305) solder and developed a new resin which can endure high temperature process so that a cleaning process can be performed after the bumping process. This SBM with SAC solder has the same features as the SBM with low-melting-point solder (3). The characteristics of the resin with and without solder were analyzed using differential scanning calorimetry (DSC) and a dynamic mechanical analyzer (DMA). The wetting behavior of SAC305 solder in the resin on Au finish and Cu finish electrodes was observed. Finally, an SAC solder bump array with pitch of 150 µm in one direction was formed using the SBM with SAC, and its morphologies were characterized.

In this paper, we present the fabrication of 40 Gb/s traveling-wave electroabsorption modulator-integrated laser (TW-EML) modules. A selective area growth method is first employed in 40 Gb/s EML fabrication to simultaneously provide active layers for lasers and modulators. The 3 dB bandwidth of a TW-EML module is measured to be 34 GHz, which is wider than that of a lumped EML module. The 40 Gb/s non-return-to-zero eye diagram shows clear openings with an average output power of +0.5 dBm.

Integration of a 40-Gb/s electroabsorption modulator integrated distributed feedback (DFB) laser (EML) module with a driver amplifier and bias tee was investigated. For the EML fabrication the selective area growth (SAG) technique was adopted for the first time. It is shown that, with the SAG technique, the 3-dB bandwidth of about 45 GHz was measured in the electrical to optical response, and the return loss (S11) of below -10 dB was achieved for up to 50 GHz . To integrate a bias tee within the module, a right-angle bent coplanar waveguide (CPW) was developed. The right-angle bent CPW was characterized with S11 of below - 10 dB for up to 35 GHz and insertion loss (S21) of about -1.4 dB for up to 40 GHz . The whole integrated module including the EML, a driver amplifier, and bias tee was characterized under the conditions of an operating temperature of 25degC, the modulator bias of 1.4 V, and the DFB laser current of 40 mA. S11 of below -10 dB was obtained for up to 14 GHz and the measured electrical-to-optical response has 3-dB bandwidth of about 20 GHz.

We have developed 40-Gb/s traveling-wave electroabsorption-modulator-integrated distributed feedback laser (TW-EML) modules using several advanced technologies. First, we have adopted a selective area growth (SAG) method in the fabrication of the 40-Gb/s EML device to provide active layers for the laser and the electroabsorption modulators (EAMs) simultaneously. The fabricated device shows that the measured 3-dB bandwidth of electrical-to-optical (E/O) response reaches about 45 GHz and the return loss (S11) is kept below -10 dB up to 50 GHz. For the module design of the device, we mainly considered electrical and optical factors. The measured S11 of the fabricated 40 Gb/s TW-EML module is below -10 dB up to about 30 GHz and the 3-dB bandwidth of the E/O response reaches over 35 GHz. We also have developed two types of coplanar waveguide (CPW) for the application of the driver amplifier integrated 40 Gb/s TW-EML module, which is a system-on-package (SoP) composed of an EML device and a driver amplifier device in a module. The measured S11 of the two-step-bent CPW is below -10 dB up to 35 GHz and the measured S11 of the parallel type CPW is below -10 dB up to 39 GHz.

A system-on-packaging (SoP) with an electroabsorption modulator (EAM) for a 60 GHz band radio-over-fiber (RoF) link is described. The system consists of an EAM device, a microstrip filter, and a low noise amplifier (LNA). The microstrip filter was used to achieve impedance matching between the EAM device and the LNA and to reject the local oscillator (LO) frequency of the heterodyne system. The frequency response and the effect of the EAM bias voltage were measured for a simple RF/optical link. A 60 GHz band RoF link with 2.5 GHz intermediate frequency (IF) was prepared to measure the transmission characteristics of the 16 QAM data.

Using an electro-absorption duplexer (EAD) we presented a transceiver (TRx) module for dual function of both electrical-to-optical (E/O) and optical-to-electrical (E/O) conversion at 60 GHz band. The EAD chip was fabricated by monolithically integrating both a waveguide photodiode (PD) and an electro-absorption modulator (EAM) in association with traveling wave electrodes. We also investigated the issues of RF packaging in which the optoelectronic and electronic amplifier devices were co-packaged in a single housing. The RF impedance matching was accomplished in assistance with a microstrip bandpass filter.

In this letter we present a right-angle-bent coplanar waveguide (CPW) which we developed for the application of the driver amplifier-integrated (DAI) 40 Gbps traveling wave electroabsorption modulated laser module. The developed CPW realized parallel progression of the radio frequency (RF) and light using a dielectric overlay structure and wedge bonding on the bending section. The measured S11 and S21 of the developed CPW were kept below -10 dB up to 35 GHz and -3 dB up to 43 GHz, respectively. These measured results of the CPW were in good agreement with the simulation results and demonstrated the applicability of the CPW to the 40 Gbps communication module.

We developed high-speed optoelectronics packaging technologies for a waveguide photodiode and a traveling wave electro-absorption modulator device for 40-Gb/s digital communication systems. The effects of the device and the packaging designs on the broadband performance were investigated to optimize broadband characteristics. For the receiver, inductive peaking was used for bandwidth control and an internal bias tee was implemented; in addition, two types of preamplifier devices were used to develop high-gain receiver and wide-bandwidth receiver. In the optical-to-electrical response, a 3-dB bandwidth of the high-gain module was about 32 GHz as compared to 42 GHz for the wide-bandwidth module. The clear 40-Gb/s nonreturn-to-zero (NRZ) eye diagrams showed a good system applicability of these modules. In addition, an optimized modulator module showed a 3-dB bandwidth of 38 GHz in the electrical-to-optical response, an electrical return loss of less than 10 dB at up to 26 GHz, an rms jitter of 1.832 ps, and an extinction ratio of 5.38 dB in a 40-Gb/s NRZ eye diagram

This letter proposes a new impedance matching scheme of a traveling wave electro-absorption modulator (TWEAM) module for a 60 GHz band radio-over- fiber (ROF) link. A microstrip band pass filter (BPF) was used to achieve impedance matching at the 60 GHz band, and termination resistance was carefully designed to obtain an input impedance close to 50 Ω.. Also, a bias circuit for the device was designed in the module. The measured return loss and frequency response show that the modulator module observes the characteristics of a filter without the need of a further tuning process.

We developed an analog 60-GHz module for RF/optic conversion by using an electroabsorption modulator (EAM) device associated with a traveling-wave electrode. The impedance matching of the module was accomplished with the 30-/spl Omega/ termination such that the resonance was precisely located at 60 GHz and the fractional bandwidth at S/sub 11/=-15 dB was as large as 1.0 GHz. The RF/optic conversion gain of the EAM device revealed a strong dependence on the input optical power and was closely related with the slope change in the optical transmission characteristic with reverse bias. From the EAM module with the composite-type multiple-quantum-well electroabsorption core consisting of both 8- and 12-nm quantum wells, we obtained the optimal RF/optic conversion gain at the reverse bias between 1.5-2 V in a wide range of input optical power from -6 to +9 dBm. In the same bias range, the third-order intermodulation distortion was

In this study, scattering from a general high-order inhomogeneousimpedance cylinder is investigated by series expansion of the surface impedance for an incident TM wave. A similar procedure can also be applied for the TE incidence case. It is observed that when N increases, the results converge more rapidly. The proposed method and the MoM technique are also applied for a 1 st -order inhomogeneous impedance cylinder. The obtained results are compared by those obtained using the numeric MoM technique and good agreement is observed. The proposed method also significantly reduces the computer calculation time according the MoM. For instance, using the same computer, the calculation times of Figure 2 by proposed method with N 30 coefficients and discretization number N 400 points (MoM) are 3.859 and 38.65 s, respectively. REFERENCES

We fabricated 40 Gb/s front-end optical receivers using spot-size converter integrated waveguide photodiodes (SSC-WGPDs). The fabricated SSC-WGPD chips showed a high responsivity of approximately 0.8 A/W and a 3 dB bandwidth of approximately 40 GHz. A selective wetetching method was first adopted to realize the required width and depth of a tapered waveguide. Two types of electrical pre-amplifier chips were used in our study. One has higher gain and the other has a broader bandwidth. The 3 dB bandwidths of the higher gain and broader bandwidth modules were about 32 and 42 GHz, respectively. Clear 40 Gb/s non-return-to-zero (NRZ) eye diagrams showed good system applicability of these modules.

Packaging technologies for a broadband and narrowband modulator with a traveling wave electro-absorption modulator (TWEAM) device were developed. In developing a broadband modulator, the effects of the device and packaging designs on the broadband performance were investigated. The optimized designs were obtained through a simulation with the result that we developed a broadband modulator with a 3 dB bandwidth of 38 GHz in the electrical-to-optical (E/O) response, an electrical return loss of less than -10 dB at up to 26 GHz, an rms jitter of 1.832 ps, and an extinction ratio of 5.38 dB in a 40 Gbps non-return to zero (NRZ) eye diagram. For analog application, the effect of the RF termination scheme on the fractional bandwidth was studied. The microstrip line with a double stub as a matching circuit and a laser trimming process were used to obtain an S 1 1 of -34.58 dB at 40 GHz and 2.9 GHz bandwidth of less than -15 dB.

Reaction characteristics of the In-15Pb-5Ag (wt.%) solder with a Au/Ni/Cu pad during reflow soldering and aging treatment were examined. Interfacial reaction during reflow resulted in either an AuIn2 or Ni28In72 layer, depending on reflow time. The AuIn2 layer became thinner and disappeared from the interface, and only the Ni28In72 layer grew with the progress of aging treatment at 130°C. Based on those observations, the dissolution rate of the Au top layer was estimated, and the behavior of the AuIn2 layer during reflow and aging treatment was discussed. In addition, peak shear load and fracture energy of the solder bump were measured as a function of reflow time and aging treatment. The results were compared with those measured with the Sn-37Pb solder bump.

A novel, maskless, low-volume bumping material, called solder bump maker, which is composed of a resin and lowmelting-point solder powder, has been developed. The resin features no distinct chemical reactions preventing the rheological coalescence of the solder, a deoxidation of the oxide layer on the solder powder for wetting on the pad at the solder melting point, and no major weight loss caused by outgassing. With these characteristics, the solder was successfully wetted onto a metal pad and formed a uniform solder bump array with pitches of 120 μm and 150 µm.

Copper lead frame was chosen as an on-board reliability enhancement for the BLP (bottom leaded plastic) package. Adopting the copper lead frame needed a verification process for the package reliability because of its high affinity with oxygen that degrades package reliability. A series of tests were performed to select the best copper material and to determine the adhesion index parameter. The experimental results showed that the adhesion strength between the copper lead frame and EMC (epoxy molding compound) was affected by alloy composition, oxide layer thickness, and cupric/cuprous oxide ratio, Among them, the adhesion index parameter proved to be the cupric/cuprous oxide ratio. When it falls between 0.2-0.3, the highest adhesion strength was obtained regardless of alloy composition and oxide thickness. From the adhesion test results, the Cr-Zr-Cu copper alloy was employed as the lead frame for the 54-pin BLP package. The package reliability and on-board reliability tests including surface mountability, mechanical robustness, and solder joint reliability were carried out to compare the 54-pin BLP package, with Cr-Zr copper alloy and alloy 42 lead frame.

Harmonic signal generation and frequency up-conversion are demonstrated using a hybrid mode-locked multisection distributed-feedback (MS-DFB) laser. Hybrid mode-locking is realized by direct injection of electrical local oscillator (LO) signals into the laser gain control section. The harmonic signals are generated when multiple optical modes produced by the hybrid mode-locked MS-DFB laser are detected in a photodiode (PD). In addition, if data signals at fIF are applied to the device along with LO signals at fLO, optical sidebands separated from the optical modes by fIF are generated and harmonic up-converted signals are obtained by mode-beating in PD. Using this method, we demonstrate generation of the third-harmonic millimeter-waves at 30.79 GHz with fLO at 10.263 GHz, and up-conversion of 12.5-Mb/s 32 quadrature amplitude modulation data at 300-MHz fIF into 30-GHz band

A sampled-grating distributed Bragg reflector laser module having an integrated multiwavelength locker has been developed and evaluated. The uniquely designed wavelength locker made of thermally controlled etalon has provided uniform wavelength monitoring and very stable wavelength locking in the 188-ITU grid channels (37 nm) with 25-GHz spacing. Over the case temperature from -5/spl deg/C to 65/spl deg/C, the laser wavelength was locked within /spl plusmn/0.5 GHz, and the total power consumption of the module was less than 4 W.

As the operating frequency of systems increases above the gigahertz frequency range, the electrical performance of a package becomes more critical. Wafer level package (WLP) is a promising solution for future high-speed packaging needs. Because the length of the interconnection lines on the WLP is limited to die size, the WLP has a minimum number of electrical parasitic elements. Because the crosstalk generates significant unwanted noise in nearby lines, causing problems of skew, delay, logic faults, and radiated emission, the crosstalk phenomena is drawing more attention than ever among the electrical characteristics of the WLP. Consequently, the modeling of the crosstalk parameters of the WLP is very important when used in high-speed systems. In this paper, we first report the crosstalk model parameters of the WLP, especially for the redistribution layer. These can be easily embedded into SPICE circuit simulation. The model is represented by the distributed lumped circuit elements, such as the mutual capacitance and the mutual inductance. The crosstalk model was extracted from two-step on-wafer S-parameter measurements and was fitted to the measurements made at up to 5 GHz.

We have developed a system-on-packaging (SoP) module with a spot size converter integrated electro-absorption duplexer (EAD) device for 60 GHz band radio-over-fiber link (RoF). The design of the EAD device is described, and its performances such as optical, electrical characteristics, crosstalk and alignment tolerance are investigated. The fiber-to-fiber insertion loss and the extinction ratio of the EAD were 15.74 dB at 0 V and 7.43 dB at −5 Vdc, respectively. The electrical S11 was smaller than −15 dB, and S21 was larger than −3 dB up to 60 GHz.