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In this article, a half-bridge class-D audio amplifier (HB-CDAA) system with embedded bidirectional buck–boost converter is proposed. The proposed HB-CDAA system consists of a front-end symmetric bipolar output converter, a bidirectional buck–boost converter, and an HB-CDAA. With the help of the embedded bidirectional buck–boost converter, bus voltage pumping on the output of the front-end symmetric bipolar output converter of HB-CDAA can be suppressed. Thus, small ceramic capacitors can be used as bus capacitors to increase power density and to improve audio output quality. Furthermore, ZVS of the embedded bidirectional buck–boost converter can be achieved. The operating principle of the proposed circuit is analyzed and an experimental prototype is built. Experimental results show that ZVS of the embedded bidirectional buck–boost converter is achieved, and bus voltage pumping is successfully suppressed with small bus capacitors.

Pulse train (PT) control strategy for the boost power factor correction (PFC) converter operating in the continuous conduction mode (CCM) is proposed and studied in this article. Average current mode (ACM) control is usually utilized for the CCM boost PFC converter. The ACM-controlled PFC converter suffers from poor dynamic response, because its voltage control loop has to be designed with low bandwidth to minimize the effect of low-frequency output voltage ripple on the current control loop. Different from ACM control, the voltage control loop and current control loop of the PT-controlled PFC converter are decoupled, and thus the effect of low-frequency output voltage ripple on the current control loop is eliminated. Besides, PT modulation is utilized in the proposed controller to regulate the inductor current to follow the current reference. Thus, both high power factor and fast dynamic response can be achieved. The operation principle of the PT-controlled CCM boost PFC converter is analyzed, and a 300-W prototype is built to verify the analysis results. The experimental results show that power factor of the PT-controlled PFC converter is higher than 0.998 and the dynamic response is significantly improved.

Being one non-orthogonal multiple access (NOMA) scheme, interleave-division multiple access (IDMA) can increase the capacity of wireless communication, and therefore, has drawn a lot of attention. Combined with orthogonal frequency division multiplexing (OFDM), OFDM-IDMA system demonstrates good performance with low complexity. In this paper, polar codes are applied to OFDM-IDMA for further performance improvement due to its capacity-achieving capability. The corresponding joint detection and decoding (JDD) scheme is proposed as well. A sign-aided JDD (SA-JDD) scheme is introduced for better efficiency. According to numerical results, the proposed JDD scheme has 1.2 dB performance gain over the separated detection and decoding (SDD) scheme when FER is 10−2. Compared to JDD, SA-JDD scheme reduces the computational complexity by 50% without performance degradation when SNR is 6 dB. In addition, approximation strategy and folding technique are applied for hardware-friendly implementation. The ASIC implementation has demonstrated the advantages of SA-JDD.

A single-stage ac–dc converter with high power factor (PF) usually suffers from a significant output voltage ripple at double line frequency. In order to suppress such low-frequency output voltage ripple and maintain high PF, a series compensation circuit (SCC), which generates the same magnitude but 180° phase shifted low-frequency voltage ripple, is connected in series with the output of a power factor correction (PFC) converter. In this paper, an output impedance model of the SCC is established and the relationship between the output impedance of the SCC and the low-frequency output voltage ripple of an ac–dc converter is analyzed. Based on the proposed output impedance model, a low-frequency output voltage ripple can be evaluated. To further reduce the low-frequency output voltage ripple, an output impedance shaping method with a virtual impedance is presented. The implementation of the virtual impedance of the SCC with average current mode control is studied. A flyback PFC converter with a buck SCC is implemented for the study of the suppression of the low-frequency output voltage ripple. A prototype is designed to verify the analysis results.

In this paper, a digital-based pulse train (PT) control technique for a boost power factor correction (PFC) converter operating in a discontinuous conduction mode (DCM) is presented, which can achieve nearly unity power factor (PF) over a universal input voltage range. Different from traditional digital control techniques, which usually require complex arithmetic operations, the digital-based PT control technique only needs a simple operation. Besides, a DCM boost PFC converter with digital PT control can operate at a high switching frequency, which is less dependent on the processing speed of a digital controller. Thus, the proposed control strategy can be implemented with general purpose digital controllers, such as low-speed and low-cost microcontroller unit, for the DCM boost PFC converter where the cost is a focus. The operation principle of the digital PT controlled DCM boost PFC converter is analyzed. Experimental results are provided, which show that high PF and low input current total harmonic distortion can be maintained over a universal input voltage range of 90–264 V ac.

The influence of a filter inductor on the steady-state performance of a parallel-type resonant converter is elaborated and analyzed in this paper. By steady-state operation analysis, it is shown that the ripple current of the filter inductor results in an inaccurate prediction of fundamental harmonic approximation (FHA), and such problem would become serious when the filter inductance is small. In order to portray such feature, an improved fundamental harmonic approximation (IFHA) is proposed. Unlike an FHA equivalent circuit, an equivalent inductor is added to the ac resistance parallelly in an IFHA equivalent circuit. Due to that, the equivalent inductor branch takes account of the ripple current of the filter inductor, and the IFHA is expected to own higher accuracy and can be used in a parameter design procedure. In this paper, the equivalent inductor expressions of full-bridge rectifier and current-doubler rectifier are derived as examples. In order to verify the theoretical analysis, a 500 W LCC resonant converter is built as a prototype. The close-loop experiment results show that small filter inductance would lead to the failure of output voltage regulation and hard-switching operation of power switches. And open-loop experiment results show the IFHA gives more accurate predictions than those of FHA.

Quasi-cyclic (QC) low-density parity-check (LDPC) codes have become popular in NAND flash memories, owing to their excellent error correction performance and hardware-friendly structures. However, the large scale of barrel shifters result in prohibitive routing complexity. Array LDPC code is a kind of highly structured QC-LDPC code, which provides a good balance of performance, complexity, and throughput. In this brief, a construction method of dispersed array LDPC (DA-LDPC) codes based on an array square is proposed. DA-LDPC codes not only benefit from the array property but also a hybrid and efficient storage architecture due to their stair-like structure. For NAND flash applications, the code construction and decoder architecture of a (18300, 16470) DA-LDPC code is illustrated in this brief, where a two-level decision of LDPC decoding strategy is employed. The numerical results based on an FPGA emulation platform have shown that the error floor of the (18300, 16470) DA-LDPC code is under 10−11 in term of bit error rate (BER). Thanks to the well-structured DA-LDPC codes, we can conveniently apply a column-based shuffle decoding (CBSD) algorithm for ease of implementation. The corresponding ASIC implementation results have proved that the decoder architecture of DA-LDPC codes can achieve higher normalized-throughput-gate-count-ratio (NTGR) compared to state-of-art works.

Graphics processing units (GPUs) are well-suited for decoding low-density parity-check (LDPC) codes because of their massive parallelisms and high flexibility. Implementations of high-throughput GPU-based LDPC decoders are described in this letter. By applying a novel message updating scheme and reducing shared memory consumption, the flooding-based and layered-based decoders outperform the corresponding state-of-the-art designs, with 55% and 34% improvements of normalized throughputs. On a single GeForce GTX 1080 Ti GPU, the two decoders achieve 4.77- and 3.67-Gb/s throughputs by incorporating early termination criterion. Throughputs of the GPU-based decoders are comparable with an implementation on the largest density field-programmable gate array.

Linear feedback shift register (LFSR) has been widely applied in BCH and CRC encoding. In order to increase the system throughput, the parallelization of LFSR is usually needed. Previously, a technique named state-space transformation was presented to reduce the complexity of parallel LFSR architectures. Exhaustive searches are performed to find good transformation matrix candidates. This brief proposes a new technique for construction of the transformation matrix together with a more efficient searching algorithm. The realization results indicate that the proposed architecture outperforms the prior arts, improving the hardware efficiency by around 35% and the corresponding searching algorithm finds the desirable transformation matrix much faster.

Micro-structured pressure sensors with broad pressure sensing range, high sensitivity and rapid response speeds are highly desired for epidermal electronic skin. The widely used methods to fabricate micro-structured pressure sensors are lithography and biomaterial-replicating, which are either complex in preparation procedure or uncontrollable in micro-structure morphology. In this work, laser micro-structured wearable pressure sensors with high-performance are developed for epidermal electronic skin. Laser micro-engineering, with scalability, high-efficiency, and controllability, is employed to prepare a series of micro-structures on elastomers for modulating and enhancing the sensitivity of the sensors. The device with micro-domes owns a sensitivity of -1.82 kPa-1, which is approximately 17 times better than the one based on long micro-ridges. Due to the reduced viscous properties of the elastomers by laser micro-engineering, the sensor based on micro-domes demonstrates rapid response/relaxation speeds of 0.036 and 0.052 s, respectively, and a detection limit of 0.001 kPa. Additionally, the device has a good durability (6,000 cycles) with a repeatability deviation of 1.44%, confirming its stability. Combined with near field communication technology, the sensor has been investigated as epidermal electronic skin for health monitoring.

A network access selection algorithm based on the intuitionistic fuzzy analytic hierarchy process (AHP) and bilateral profit drive is proposed in this study for addressing problems regarding user–network bilateral profits. User preference, business demands, and network parameter changes are comprehensively considered in the algorithm. First, the initial weights centered at users are gained by intuitionistic fuzzy AHP. Second, the network participates in network access selection as a subject with competitive consciousness, and the entire selection process is transformed into a multiobjective optimization problem by the construction of a competitive model, thereby obtaining dynamic competitive weights. Third, the initial weights centered at users and the dynamic competitive weights are combined to obtain comprehensive weights. In this way, the dynamic adjustment of comprehensive weights is realized. Finally, candidate networks are ordered according to a comprehensive performance evaluation, and the optimal one is selected. The proposed algorithm is validated by simulation results to be valid in reducing the blocking rate of networks and optimizing network resource allocation. Therefore, it not only protects user–network bilateral profits but also maximizes comprehensive profits.

Massive multiple input multiple output (M-MIMO) is an enabling technology of 5G wireless communication. The performance of an M-MIMO system is highly dependent on the speed and accuracy of obtaining the channel-state information. The computational complexity of channel estimation for an M-MIMO system can be reduced by making use of the sparsity of the M-MIMO channel. In this paper, we propose the hardware-efficient channel estimator based on angle-division multiple access for the first time. Preamble, uplink, and downlink training are also implemented. For further hardware-efficiency consideration, optimization regarding quantization and approximation strategies has been discussed. Implementation techniques, such as pipelining and systolic processing, are also employed for hardware regularity. Numerical results and field-programmable gate array implementation have demonstrated the advantages of the proposed channel estimator.

Polar codes have become increasingly popular recently because of their capacity achieving property. In this paper, a memory efficient stage-combined belief propagation (BP) decoder design for polar codes is presented. Firstly, we briefly reviewed the conventional BP decoding algorithm. Then a stage-combined BP decoding algorithm which combines two adjacent stages into one stage and the corresponding belief message updating rules are introduced. Based on this stage-combined decoding algorithm, a memory-efficient polar BP decoder is designed. The demonstrated decoder design achieves 50% memory and decoding latency reduction in the cost of some combinational logic complexity overhead. The proposed decoder is synthesized under TSMC 45nm Low Power CMOS technology. It achieves 0.96 Gb/s throughput with 14.2mm2 area when code length N=216 which reduces 51.5% decoder area compared with the conventional decoder design.

Pulse train (PT) control technique realizes the output voltage regulation of switching dc-dc converters by using preset high power control pulse P H and low power control pulse P L . In steady state, P H and P L in some successive switching cycles constitute a control pulse repetition cycle. The control pulse combination of PH and P L in the control pulse repetition cycle has a significant effect on the performances of PT controlled switching dc-dc converters. In this paper, by taking PT controlled discontinuous conduction mode buck converter as an example, the control pulse combination of PT controlled buck converter is studied. Some lemmas to reveal the control pulse combination are presented, and the combination of P H and P L in a control pulse repetition cycle is obtained. Based on which, the steady-state and transient performances of PT controlled buck converter are investigated. The control pulse combination-based analysis of PT controlled buck converter provides an effective way to understand the PT control technique in detail.

This paper studies the effects of the covering layers on the performance of a cross-like Hall plate. Three different structures of a cross-like Hall plate in various sizes are designed and analyzed. The Hall plate sensitivity and offset are characterized using a self-built measurement system. The effect of the P-type region over the active area on the current-related sensitivity is studied for different Hall plate designs. In addition, the correlation between the P-type covering layer and offset is analyzed. The best structure out of three designs is determined. Besides, a modified eight-resistor circuit model for the Hall plate is presented with improved accuracy by taking the offset into account.

Since the polar code was discovered by Arikan, many decoding methods have been proposed, one of which is the belief propagation (BP) decoding. Its inherent high parallel level makes it suitable for high-speed applications. A novel BP decoder based on a modified three-by-three kernel matrix is proposed. The corresponding decoding algorithm and frozen bits selection method are presented. The numerical results show that it has a similar error correcting capability compared with the original polar BP decoder. More importantly, the message memory requirement can be reduced from O ( N log 2 N ) to O ( N log 3 N ), and the decoding delay can be reduced accordingly.

A variable on-time (VOT) control strategy for a critical conduction mode (CRM) flyback power factor correction (PFC) converter with low total harmonic distortion (THD) and high power factor (PF) is proposed in this paper. By using input voltage and the voltage across the auxiliary winding of the flyback transformer to modulate the turn-on time of the switch of the CRM flyback PFC converter, the PF and THD of the converter can be improved. The operation principles of the traditional constant on-time (COT)-controlled CRM flyback PFC converter and VOT-controlled CRM flyback PFC converter are analyzed. The experimental results show that the PF and THD of the VOT-controlled CRM flyback PFC converter are better than those of the COT-controlled CRM flyback PFC converter.

Current-mode pulse train (CMPT) control technique, a novel discrete control technique for switching dc-dc converters, has completely different dynamics from the traditional pulsewidth modulation control technique. In this paper, a 1-D normal form of discrete-time map of CMPT-controlled buck converter operating in discontinuous conduction mode (DCM) is established, upon which the effects of the circuit parameters on the dynamics and the border collision bifurcation behaviors of CMPT-controlled DCM buck converter are observed and analyzed. According to discrete iterative maps of period-1, period-2, and period-3, the fixed point analyses of the corresponding periodicities are studied, and the mechanism of border collision bifurcation is revealed. Simultaneously, the parameter conditions of different periodicities are formulated, which are helpful to better understand the behaviors and to analyze the CMPT-controlled buck converter.

Reed-Solomon (RS) codes are widely used as forward correction codes (FEC) in digital communication and storage systems. Correcting random errors of RS codes have been extensively studied in both academia and industry. However, for burst-error correction, the research is still quite limited due to its ultra high computation complexity. In this brief, starting from a recent theoretical work, a low-complexity reformulated inversionless burst-error correcting (RiBC) algorithm is developed for practical applications. Then, based on the proposed algorithm, a unified VLSI architecture that is capable of correcting burst errors, as well as random errors and erasures, is firstly presented for multi-mode decoding requirements. This new architecture is denoted as unified hybrid decoding (UHD) architecture. It will be shown that, being the first RS decoder owning enhanced burst-error correcting capability, it can achieve significantly improved error correcting capability than traditional hard-decision decoding (HDD) design.

Nonbinary low-density parity-check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity iterative decoding algorithms have been proposed, the VLSI implementation of NB-LDPC decoders still remains a big challenge due to its high complexity and long latency. In this brief, a highly efficient check node processing scheme, which the processing delay greatly reduced, is proposed for Min-max decoding algorithm. Thereafter, an efficient check node unit (CNU) can be designed. Compared with previous works, the latency of the CNU could be reduced to less than 52%. In addition, a decoder for a (620, 310) NB-LDPC code is designed to demonstrate the efficiency of the presented techniques.

This work studies the effects of an aluminum covering on the performance of cross-like Hall devices. Four different Hall sensor structures of various sizes were designed and fabricated. The sensitivity and offset of the Hall sensors, two key points impacting their performance, were characterized using a self-built measurement system. The work analyzes the influences of the aluminum covering on those two aspects of the performance. The aluminum layer covering mainly leads to an eddy-current effect in an unstable magnetic field and an additional depletion region above the active region. Those two points have influences on the sensitivity and the offset voltage, respectively. The analysis guides the designer whether to choose covering with an aluminum layer the active region of the Hall sensor as a method to reduce the flicker noise and to improve the stability of the Hall sensor. Because Hall devices, as a reference element, always suffer from a large dispersion, improving their stability is a crucial issue.

Low-Density Parity-check (LDPC) code, being one of the most promising near-Shannon limit error correction codes (ECCs) in practice, has attracted tremendous attention in both academia and industry since its rediscovery in middle 1990's. Owning excellent coding gain, LDPC code also has very low error floor, and inherent parallizable decoding schemes. Compared to other ECCs such as Turbo codes, BCH codes and RS codes, LDPC code has many more varieties in code construction, which result in various optimum decoding architectures associated with different structures of the parity-check matrix. In this work, we first provide an overview of typical LDPC code structures and commonly-used LDPC decoding algorithms. We then discuss efficient VLSI architectures for random-like codes and structured LDPC codes. We further present layered decoding schemes and corresponding VLSI architectures. Finally we briefly address non-binary LDPC decoding and multi-rate LDPC decoder design.

This paper addresses decoder design for nonbinary quasicyclic low-density parity-check (QC-LDPC) codes. First, a novel decoding algorithm is proposed to eliminate the multiplications over Galois field for check node processing. Then, a partially parallel architecture for check node processing units and an optimized architecture for variable node processing units are developed based on the new decoding algorithm. Thereafter, an efficient decoder structure dedicated to a promising class of high-performance nonbinary QC-LDPC codes is presented for the first time. Moreover, an ASIC implementation for a (620, 310) nonbinary QC-LDPC code decoder over GF(32) is designed to demonstrate the efficiency of the presented techniques.

Low-density parity-check (LDPC) codes constructed over the Galois field GF(q), which are also called nonbinary LDPC codes, are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity quasi-optimal iterative decoding algorithms have been proposed, the VLSI implementation of nonbinary LDPC decoders has rarely been discussed due to their hardware unfriendly properties. In this brief, an efficient selective computation algorithm, which totally avoids the sorting process, is proposed for Min-Max decoding. In addition, an efficient VLSI architecture for a nonbinary Min-Max decoder is presented. The synthesis results are given to demonstrate the efficiency of the proposed techniques.

Low-density parity-check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. However, the efficient implementation of high-throughput LDPC decoders adaptable for various channel conditions still remains challenging. In this paper, a low-complexity reconfigurable VLSI architecture for high-speed LDPC decoders is presented. Shift-LDPC codes are incorporated within the design and have shown not only comparable decoding performance to computer-generated random codes but also high hardware efficiency in high-speed applications. The single-minimum Min-Sum decoding scheme and the nonuniform quantization scheme are explored to reduce the complexity of computing core and the memory requirement. The well-known Benes network is employed to construct the configurable permutation network to support multiple shift-LDPC codes with various code parameters. The ASIC implementation results of an (8192, 7168) (4, 32)-regular shift-LDPC decoder demonstrate a maximum decoding throughput of 3.6 Gbits/s at 16 iterations, which outperforms the state-of-the-art design for high-speed flexible LDPC decoders by many times with even less hardware.

This brief studies very large-scale integration (VLSI) decoder architectures for RS-based low-density parity-check (LDPC) codes, which are a special class of LDPC codes based on Reed-Solomon codes. The considered code ensemble is well known for its excellent error-correcting performance and has been selected as the forward error correction coding scheme for 10GBase-T systems. By exploiting the shift-structured properties hidden in the algebraically generated parity-check matrices, novel decoder architectures are developed with significant advantages of high level of parallel decoding, efficient usage of memory, and low complexity of interconnection. To demonstrate the effectiveness of the proposed techniques, we completed a high-speed decoder design for a (2048, 1723) regular RS-LDPC code, which achieves 10-Gb/s throughput with only 820 000 gates. Furthermore, to support all possible RS-LDPC codes, two special cases in code construction are considered, and the corresponding extensions of the decoder architecture are investigated.

A high-speed low-complexity Reed-Solomon (RS) decoder architecture based on the recursive degree computationless modified Euclidean (rDCME) algorithm is presented in this brief. The proposed architecture has very low hardware complexity compared with the conventional modified Euclidean and degree computationless modified Euclidean (DCME) architectures, since it can reduce the degree computation circuitry and replace the conventional systolic architecture that uses many processing elements (PEs) with a recursive architecture using a single PE. A high-throughput data rate is also facilitated by employing a pipelining technique. The proposed rDCME architecture has been designed and implemented using SMIC 0.18-mum CMOS technology. Synthesized results show that the proposed RS (255, 239) decoder requires only about 18 K gates and can operate at 640 MHz to achieve a throughput of 5.1 Gb/s, which meets the requirement of modern high-speed optical communications.

This paper presents an efficient architecture for computing the eight-point 1D scaled DCT (discrete cosine transform) with a new algorithm based on a selected Loeffler DCT scheme whose multiplications are placed in the last stage. The proposed DCT architecture does not require any scaling compensation in the computation. Furthermore, a multiplication approximation method is developed, which is more efficient than traditional CORDIC (coordinate rotation digital computer)-based algorithms. Compared to the latest work (Sun et al., 2007), the proposed approach can save 14% addition operations for the same precision requirement and the path delay can be significantly reduced as well.

This paper presents two efficient decoder designs for the low-density parity-check codes in IEEE 802.15.3 standard proposal. These decoders feature by efficient hardware usage, low message memory requirement and code rate flexibility. The highly parallel level design can reach a throughput of 3.6 Gbps, which fulfills the standard requirement by processing 72 columns and 72 rows in parallel. The low cost design offers another tradeoff which significantly reduces the area and power consumption while maintaining necessary data throughput required by specific applications. Furthermore, both decoders support three different code rates by employing flexible check node processing units.

In this brief, a new algorithm that can efficiently generate all the control signals for the shuffle network used in flexible low-density parity-check (LDPC) decoders is proposed. Employing the proposed algorithm, the hardware complexity of the controller of shuffle networks using the Benes network structure can be significantly reduced. In addition, a low-complexity reconfigurable shuffle network architecture for flexible LDPC decoders is developed. Both the Benes network and the controller can be tailored to fit specific applications. Consequently, an efficient shuffle network for WiMAX LDPC decoders is presented. Synthesis results demonstrate that with the SMIC 0.18-mum complementary metal-oxide-semiconductor process, the total gate count of the proposed shuffle network is only 16 000. The area saving is between 26.6% and 71.1% compared to related works in the literature.

Low-density parity-check (LDPC) code, a very promising near-optimal error correction code (ECC), is being widely considered in next generation industry standards. The VLSI implementation of high-speed LDPC decoder remains a big challenge. This paper presents the construction of a new class of implementation-oriented LDPC codes, namely shift-LDPC codes. With girth optimization, this kind of codes can perform as well as computer generated random codes. More importantly, the decoder can be efficiently implemented to obtain very high decoding speeds. In addition, more than 50% of message memory can be generally saved over conventional partially parallel decoder architectures. We demonstrate the benefits of the proposed techniques with an application-specific integrated circuit (ASIC) design (in 0.18-mum CMOS) for a 8192-bit regular LDPC code, which can achieve 5 Gb/s throughput at 15 iterations.

It is known that the ripple-based control of a switching dc–dc converter benefits from a faster transient response than a conventional pulse width modulation (PWM) control switching dc–dc converter. However, ripple-based control switching dc–dc converters may suffer from fast-scale oscillation. In order to achieve fast transient response and ensure the stable operation of a switching dc–dc converter over a wide load range, based on a conventional pulse train (PT) control technique, a peak capacitor current PT (PCC-PT) control technique is proposed in this paper. With a buck converter as an example, the operating modes, steady-state performance, and transient respond performance of a PCC-PT controlled buck converter are presented and assessed. To eliminate fast-scale oscillation, circuit and control parameter design considerations are given. An accurate discrete iteration model of a PCC-PT controlled buck converter is established, based on which the effects of circuit parameters on the stability of the converter operating in a discontinuous current mode (DCM), mixed DCM-continuous conduction mode (CCM), and CCM are studied. Simulation and experimental results are presented to verify the analysis results.

The principles of minimized magnetic energy and voltage equilibrium have been combined with the finite element method to solve the leakage magnetic field problems coupled with an unknown ampere-turn distribution in shell-form power transformers. Based on the leakage magnetic field calculated, the eddy current and circulating current losses in the coils are further computed. The calculated results are consistent with measured values for a model of a shell-form power transformer. The above principles are applied to the windings design of a 50 MVA three-phase prototype shell-form power transformer. The calculated results show that the largest circulating current in strands of the low-voltage coils near two ends of each phase winding is greatly reduced to 11% from 98% of the rated current in each strand by placing the copper-shieldings on these ends.

This paper gives a brief description of the over quick urbanization since Chongqing, one of the biggest cities in China, has been a municipality directly under the Central Government in 1997, excessive development and exceeding increase of high-rise buildings because of its special geographical position which finally leads to the worsening of the urban outdoor thermal environment. Then, this paper makes a bright balance to the field measurement and simulated results of the wind speed field, temperature field of one multifunctional high-rise building in Chongqing university located in the city center, and the contrasted results validate the correctness of CFD in the outdoor thermal environmental simulation, expose the disadvantages of high-rise buildings on the aspects of blocking the wind field, decreasing wind speed which results in accumulation of the air-conditioning heat revolving around and periscian region where sunshine can not rip into. Finally, in order to improve the urban outdoor thermal environment near the high-rise buildings especially for the angle of natural ventilation, this paper simulates the wind environment in different architectural compositions and architectural layouts by CFD, and the simulated results show that freestyle and tower buildings which can guarantee the wind speed and take the air-conditioning heat away are much suitable and reasonable for the special Chongqing geography. These conclusions can also be used as a reference in other mountain cities, especially for the one with a great number of populations.