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We systematically investigated the wafer- bonded interfaces of p+GaAs/n+InGaAs and p+InGaAs/ n+InGaAs by using a circular transmission line method (CTLM) for the increased extraction accuracy. Based on the low-temperature bonding process at 50 °C, the bonded interfaces were successfully fabricated without degradation of the material quality. While the fabricated devices exhibited the linearly increased resistance as a function of channel distances, the p+InGaAs/n+InGaAs structure revealed the improved interfacial resistivity of $3.9\times 10^{-3} \,\, \Omega \cdot \text{cm}^{2}$ compared with $3.3\!\times \!10^{-2} \,\, \Omega \cdot \text{cm}^{2}$ of the p+GaAs/n+InGaAs. Since these values suggested good electrical properties in wafer-bonded structures, the developed wafer-bonded interfaces could be a good approach for integrating electronic and optoelectronic devices.

In this article, we have demonstrated 125-nm-gate InGaAs-on-insulator (InGaAs-OI) high-electron-mobility transistors (HEMTs) on Si substrates via wafer bonding. The highlights of this device were the i-In0.53Ga0.47As/i-InAs/i-In0.53Ga0.47As quantum-well channel for high RF performance by improving electron transport properties and the low processing temperature of 250 °C or less for monolithic 3-D integration. As a result, we obtained a current gain cutoff frequency ( ${f}_{\text {T}}$ ) of 227 GHz and a maximum oscillation frequency ( ${f}_{\text {MAX}}$ ) of 187 GHz. These results are the highest ever reported in monolithic 3-D RF transistors above ${L}_{\text {G}} = {100}$ nm. In addition, through the small-signal modeling, we have found that the impact of the back-gate (BG) on RF performances of top devices is a critical issue in M3D RF systems.

For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display, etc.) which require high-performance, small form factors, and low power consumption, heterogeneous and monolithic 3D (M3D) integration employing advanced Si CMOS technology has been intriguing. To realize the M3D-based systems, it is important to take into account the relationship between the top and bottom devices in terms of thermal budget, electrical coupling, and operability when using different materials and various processes during integration and sequential fabrication. In this paper, from this perspective, we present our recent progress of III-V devices on Si bottom devices/circuits for providing informative guidelines in RF and imaging devices. Successful fabrication of the high-performance InGaAs high electron mobility transistors (HEMTs) on the bottom ICs, with a high unity current gain cutoff frequency (fT) and unity power gain cutoff frequency (fMAX) was accomplished without substrate noise. Furthermore, the insertion of an intermediate metal plate between the top and bottom devices reduced the thermal interaction. Furthermore, the InGaAs photodetectors (PDs) were monolithically integrated on Si bottom devices without thermal damage due to low process temperature. Based on the integrated devices, we successfully evaluated the device scalability using sequential fabrication and basic readout functions of integrated circuits.

Ball grid array (BGA) packages have been characterized from one port S-parameter measurements by shorting and opening the connection on the ball side of BGA packages. Transmission line parameters (resistance, inductance and capacitance) using the /spl Gamma/ equivalent circuit model are extracted from the measured S/sub 11/ parameter. Extracted resistances are strongly dependent on frequency, but extracted inductances and capacitances are nearly constant up to 500 MHz. Extracted capacitances are well matched to those measured from an LCR meter and calculated from a three-dimensional (3-D) simulator, Capacitance in a transmission line plays an important role in electrical performance for packages so that we may model a transmission line as a single capacitor. Extracted capacitances using the single capacitor model also well represent the measured S/sub 11/. These results suggest that the single capacitor model can be efficiently used for the transmission line model in BGA packages up to 500 MHz.