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ispartof: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS vol:30 issue:11 pages:1748-1756 status: published

ispartof: IEEE PHOTONICS JOURNAL vol:14 issue:4 status: published

Analog in Memory Computing (AiMC) based neural network acceleration is a promising solution to increase the energy efficiency of deep neural networks deployment. However, the quantization requirements of these analog systems are not compatible with state-of-the-art neural network quantization techniques. Indeed, while the quantization of the weights and activations is considered by modern deep neural network quantization techniques, AiMC accelerators also impose the quantization of each Matrix Vector Multiplication (MVM) result. In most demonstrated AiMC implementations, the quantization range of MVM results is considered a fixed parameter of the accelerator. This work demonstrates that dynamic control over this quantization range is possible but also desirable for analog neural networks acceleration. An AiMC compatible quantization flow coupled with a hardware aware quantization range driving technique is introduced to fully exploit these dynamic ranges. Using CIFAR-10 and ImageNet as benchmarks, the proposed solution results in networks that are both more accurate and more robust to the inherent vulnerability of analog circuits than fixed quantization range based approaches.

ispartof: IEEE TRANSACTIONS ON NANOTECHNOLOGY vol:21 pages:367-373 status: published

Faster and cheaper computers have been constantly demanding technological and architectural improvements. However, current technology is suffering from three technology walls: leakage wall, reliability wall, and cost wall. Meanwhile, existing architecture performance is also saturating due to three well-known architecture walls: memory wall, power wall, and instruction-level parallelism (ILP) wall. Hence, a lot of novel technologies and architectures have been introduced and developed intensively. Our previous work has presented a comprehensive classification and broad overview of memory-centric computer architectures. In this article, we aim to discuss the most important classes of memory-centric architectures thoroughly and evaluate their advantages and disadvantages. Moreover, for each class, the article provides a comprehensive survey on memory-centric architectures available in the literature.

Breathing pattern has been shown to be different in chronic obstructive pulmonary disease (COPD) patients compared to healthy controls during rest and walking. In this study we evaluated respiratory parameters and the breathing variability of COPD patients as a function of their severity. Thoracic bioimpedance was acquired on 66 COPD patients during the performance of the six-minute walk test (6MWT), as well as 5 minutes before and after the test while the patients were seated, i.e. resting and recovery phases. The patients were classified by their level of airflow limitation into moderate and severe groups. We characterized the breathing patterns by evaluating common respiratory parameters using only wearable bioimpedance. Specifically, we computed the median and the coefficient of variation of the parameters during the three phases of the protocol, and evaluated the statistical differences between the two COPD severity groups. We observed significant differences between the COPD severity groups only during the sitting phases, whereas the behavior during the 6MWT was similar. Particularly, we observed an inverse relationship between breathing pattern variability and COPD severity, which may indicate that the most severely diseased patients had a more restricted breathing compared to the moderate patients. This work was supported in part by the Universities and Research Secretariat from the Ministry of Business and Knowledge/Generalitat de Catalunya under the Grant GRC 2017 SGR 01770, in part by the Agencia Estatal de Investigacion from the Spanish Ministry of Science ánd Innovation and the European Regional Development Fund, under the Grants RTI2018 098472-B-I00 and PID2021-126455OB-I00, and in part by the CERCA Programme/Generalitat de Catalunya.

Electromigration (EM) has emerged as a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM analysis works focus on the power lines. There exists a limited amount of work which analyzes EM failures in the signal lines. However, various emerging spintronic-based memory technologies such as the Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) and the Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) have high current densities as compared to the conventional Static Random Access Memory (SRAM). These high current densities can lead to EM failures in the signal lines such as bit-line (BL) of these memories. Furthermore, these signal lines have workload-dependent stress as opposed to the conventional DC stress of power distribution networks. In this work, we model the EM failures in the BL of a typical STT memory array with realistic workloads. The analysis is based on physics-based EM model, which is calibrated based on industrial measurement data. The results show that the current densities in the STT arrays can be large enough to cause EM failures in the signal lines with running realistic workloads and that these failures are highly workload-dependent.

ispartof: IEEE TRANSACTIONS ON ELECTRON DEVICES vol:69 issue:6 pages:3113-3117 status: published

Due to the complexity of device processing, the trade-off between yield and area has resulted in diminishing rate of scaling for the high-density static random access memory (SRAM) cell at advanced CMOS nodes. An introduction of extreme ultraviolet (EUV) and multipatterning has added additional cost to technology in order to realize 3-D device structure and ultrascaled metal routing. In this era, spin-transfer torque (STT)-MRAM technology can provide an alternative to high-density SRAM and for the last level cache (LLC) applications. In this article, we discuss the memory design and technology tradeoff to enable the STT-MRAM as a viable option. We have realized the technology over 300-mm wafer, measuring 1 million samples to build a SPICE model for circuit simulation. Occupying up to 83.3% of an area that of SRAM macro has been designed and simulated for the scaled 5-nm CMOS node. The simulated MRAM macro shows the best read and write access time of 3.1 and 6.2 ns, respectively. Magnetic tunneling junction (MTJ) pillar of 38-nm diameter is realized at 90-nm pitch, measuring resistance area (RA) of 5.2- $\Omega \cdot \mu \text{m}^{2}$ , ${J}_{sw}$ of 5.5 MA/cm2 with improved $\Delta $ avg of 70, and breakdown voltage of 0.99 V. The energy comparison shows increasing gains versus SRAM for the increasing cache sizes crossing over at of 0.3 and 4 MB for the single-cycle read and write operations, respectively.

The Fast Fourier Transform (FFT) is an efficient algorithm widely used in digital signal processing to transform between the time domain and the frequency domain. For fixed-point VLSI implementations, dynamic range growth inevitably occurs at each stage of the FFT operation. However, current methods either waste bitwidth or consume excessive resources when dealing with the dynamic range growth issue. To address this issue, we propose an efficient scaling method called Scaling Information Propagation (SIP) to alleviate the problem of dynamic range growth, which makes full use of bitwidth with much less extra area consumed than the state-of-the-art solutions. In two consecutive transform operations, the SIP method extracts scaling information and makes scaling decisions in the former transform, then executes those in the latter one. We implement the FFT's VLSI architecture in the orthogonal frequency division multiplexing (OFDM) and the holographic video compression (HVC) systems to verify the SIP method. Compared to the state-of-the-art, experimental results after VLSI synthesis show that our method achieves 9.38% energy reduction and 8.36% area savings when requiring 1.02 × 10-7 bit error ratio (BER) of the OFDM system, and 33.47% energy reduction and 30.98% area savings when requiring 20dB signal-to-noise ratio (SNR) of the HVC system, respectively.

Monolithic 3-D IC (M3-D) is a promising solution to improve the performance and energy-efficiency of modern processors. But, designers are faced with challenges in design tools and methodologies, especially for power and thermal verifications. We developed a new physical design flow that optimally places and routes cache modules in one tier and logic gates in the other. Our tool also builds high-quality clock and power delivery networks targeting logic-on-memory M3-D designs. Finally, we developed a sign-off analysis tool flow to evaluate power, performance, area (PPA), thermal, and voltage-drop quality for given M3-D designs. Using our complete register transfer level (RTL)-to-Graphic Design System (GDS) tool flow, we designed commercial quality 2-D and M3-D implementation of Arm Cortex-A7 and Cortex-A53 processors in a commercial 28-nm technology. Experimental results show that our 3-D processors offer 20% (A7) and 21% (A53) performance gain, compared with their 2-D commercial counterparts. The voltage-drop degradation of our 3-D Cortex-A7 and Cortex-A53 processors is less than 3% of the supply voltage, while temperature increase is 10.71 °C and 13.04 °C, respectively.

© 2018 Elsevier B.V. Application requirements along with the unceasing demand for ever-higher scale of device integration, has driven technology towards an aggressive downscaling of transistor dimensions. This development is confronted with variability challenges, mainly the growing susceptibility to time-zero and time-dependent variations. To model such threats and estimate their impact on a system's operation, the reliability community has focused largely on Monte Carlo-based simulations and methodologies. When assessing yield and failure probability metrics, an essential part of the process is to accurately capture the lower tail of a distribution. Nevertheless, the incapability of widely-used Monte Carlo techniques to achieve such a task has been identified and recently, state-of-the-art methodologies focusing on a Most Probable Failure Point (MPFP) approach have been presented. However, to strictly prove the correctness of such approaches and utilize them on large scale, an examination of the concavity of the space under study is essential. To this end, we develop an MPFP methodology to estimate the failure probability of a FinFET-based SRAM cell, studying the concavity of the Static Noise Margin (SNM) while comparing the results against a Monte Carlo methodology. ispartof: INTEGRATION-THE VLSI JOURNAL vol:69 pages:111-119 ispartof: location:GREECE, Thessaloniki status: published

We propose an experimentally validated physics-based process-induced variability (PIV) aware SPICE simulation framework–enabling the estimation of performance variation due to line-edge-roughness (LER), metal-gate-granularity (MGG), random-dopant-fluctuation (RDF), and oxide-thickness-variation (OTV) at sub-20 nm technology node devices. The framework utilizes LER, RDF, OTV, and MGG defining parameters such as fin-edge correlation coefficient ( $\rho $ ), autocorrelation length ( $\Lambda $ ), grain-size (GS), $\sigma [\text {EOT}]$ , etc. as the inputs, and produces ${I}_{d} $ ,– ${V}_{g}$ distribution of ensemble size 250 as an output. We have validated the framework against 14 nm FinFET experimental data for ${I}_{d}$ ,– ${V}_{g}$ trends as well as for the threshold-voltage ( ${V}_{T}$ ), ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ), and subthreshold slope (SS) distributions for a range of device dimensions with a reasonably good match. The worst and the best case ${R}$ square errors are 0.64 and 0.98, respectively, for the validation. The very nature of the proposed framework allows the designers to use it for a vast range of process technologies. Such models are of dual importance, as it enables a PIV aware prediction of circuit-level performance, and provides a platform to estimate PIV parameters efficiently, on-par with sophisticated structural characterization tools.

Neuromorphic computing systems uses non-volatile memory (NVM) to implement high-density and low-energy synaptic storage. Elevated voltages and currents needed to operate NVMs cause aging of CMOS-based transistors in each neuron and synapse circuit in the hardware, drifting the transistor's parameters from their nominal values. Aggressive device scaling increases power density and temperature, which accelerates the aging, challenging the reliable operation of neuromorphic systems. Existing reliability-oriented techniques periodically de-stress all neuron and synapse circuits in the hardware at fixed intervals, assuming worst-case operating conditions, without actually tracking their aging at run time. To de-stress these circuits, normal operation must be interrupted, which introduces latency in spike generation and propagation, impacting the inter-spike interval and hence, performance, e.g., accuracy. We propose a new architectural technique to mitigate the aging-related reliability problems in neuromorphic systems, by designing an intelligent run-time manager (NCRTM), which dynamically destresses neuron and synapse circuits in response to the short-term aging in their CMOS transistors during the execution of machine learning workloads, with the objective of meeting a reliability target. NCRTM de-stresses these circuits only when it is absolutely necessary to do so, otherwise reducing the performance impact by scheduling de-stress operations off the critical path. We evaluate NCRTM with state-of-the-art machine learning workloads on a neuromorphic hardware. Our results demonstrate that NCRTM significantly improves the reliability of neuromorphic hardware, with marginal impact on performance., Comment: Accepted in ACM JETC

Technological and architectural improvements have been constantly required to sustain the demand of faster and cheaper computers. However, CMOS down-scaling is suffering from three technology walls: leakage wall, reliability wall, and cost wall. On top of that, a performance increase due to architectural improvements is also gradually saturating due to three well-known architecture walls: memory wall, power wall, and instruction-level parallelism (ILP) wall. Hence, a lot of research is focusing on proposing and developing new technologies and architectures. In this article, we present a comprehensive classification of memory-centric computing architectures; it is based on three metrics: computation location, level of parallelism, and used memory technology. The classification not only provides an overview of existing architectures with their pros and cons but also unifies the terminology that uniquely identifies these architectures and highlights the potential future architectures that can be further explored. Hence, it sets up a direction for future research in the field.

In this article, we provide an accurate method to determine the interlayer resistivity of 2-D layered systems by directly measuring the resistance at a mono- to bi-layer step and feeding the measurement to a distributed resistance model. We take CVD-grown few-layer graphene (up to four layers) with different twist angles ranging from AB-stacked to totally decoupled graphene as an example. Our results show that the interlayer resistivity of AB-stacked CVD grown bilayer graphene (BLG) is in the range of 50–140 $\Omega $ .m, which is two to five orders of magnitude greater than the previously reported values for AB-stacked graphite. On the other hand, twisted BLG shows an interlayer resistivity as low as ${6}~\Omega $ .m and it decreases monotonically with increasing the twist angle, suggesting that interlayer conduction is not limited by phonon scattering, as previously reported. Furthermore, the total resistance of twisted BLG was found to be about one order of magnitude lower than its AB-stacked counterpart, which might lead to lower delay and energy-delay product in twisted graphene interconnects. In addition to that, the universality of our approach allows for accurate determination of interlayer resistivity of other 2-D layered systems such as metal dichalcogenides.

© 2018 IEEE. Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets]. We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (∼3× faster while simultaneously consuming ∼3× less energy) compared to Si/SiGe FinFET. The ATOs provide

© 2018 Elsevier Ltd This paper proposes an appropriate method to estimate and mitigate the impact of aging on the read path of a high performance SRAM design; it analyzes the impact of the memory cell, and sense amplifier (SA), and their interaction. The method considers different workloads, technology nodes, and inspects both the bit-line swing (BLS) (which reflect the degradation of the cell) and the sensing delay (SD) (which reflects the degradation of the sense amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results with respect to the quantification of the aging, show for the considered SRAM read-path design that the cell degradation is marginal as compared to the sense amplifier, while the SD degradation strongly depends on the workload, supply voltage, temperature, and technology nodes (up to 41% degradation). The mitigation schemes, one targeting the cell and one the sense amplifier, confirm the same and show that sense amplifier mitigation (up to 15.2% improvement) is more effective for the SRAM read path than cell mitigation (up to 11.4% improvement). ispartof: MICROELECTRONICS RELIABILITY vol:87 pages:158-167 status: published

Modern microprocessors contain a variety of mechanisms used to mitigate errors in the logic and memory, referred to as Reliability, Availability, and Serviceability (RAS) techniques. Many of these techniques, such as component disabling, come at a performance cost. With the aggressive downscaling of device dimensions, it is reasonable to expect that chip-wide error rates will intensify in the future and perhaps vary throughout system lifetime. As a result, it is important to reclaim the temporal RAS overheads in a systematic way and enable dependable performance. The current article presents a closed-loop control scheme that actuates processor’s frequency based on detected timing interference to ensure performance dependability. The concepts of slack and deadline vulnerability factor are introduced to support the formulation of a discrete time control problem. Default application timing is derived using the system scenario methodology, the applicability of which is demonstrated through simulations. Additionally, the proposed concept is demonstrated on a real platform and application: a Proportional-Integral-Differential controller, implemented within the application, actuates the Dynamic Voltage and Frequency Scaling (DVFS) framework of the Linux kernel to effectively reclaim temporal overheads injected at runtime. The current article discusses the responsiveness and energy efficiency of the proposed performance dependability scheme. Finally, additional formulation is introduced to predict the upper bound of timing interference that can be absorbed by actuating the DVFS of any processor and is also validated on a representative reduction to practice.

Designers typically add design margins to compensate for time-zero variability (due to process variation) and time-dependent (due to, e.g., bias temperature instability) variability. These variabilities become worse with scaling, which leads to larger design margin requirements. As an alternative, mitigation schemes can be applied to counteract the variability. This paper investigates the impact of aging on the offset voltage of the memory’s sense amplifier (SA). For the analysis, the degradation of the SAs in the L1 data and instruction caches of an ARM processor is quantified while using realistic workloads extracted from the SPEC CPU2006 Benchmark suite. Furthermore, the effect of our mitigation scheme, i.e., an online control circuit that balances the SA workload, is analyzed. The simulation results show that the mitigation scheme reduces the offset voltage degradation due to aging with up to 40% for the benchmarks, depending on the stress conditions (temperature, voltage, and workload).

Extended transistor scaling has brought us a lot of benefits, but also a myriad of problems, including severe reliability issues [1] . To extend the scaling path as far as possible, system architects and technologists have to work together. They have to find solutions—e.g., at system level—to realize self-healing chips, chips that can detect or “feel” where errors occur and that know how to deal with them or in a way “cure” them. Only then will it be feasible to design systems in technologies with transistors scaled down to 5 nm dimensions.

The CMOS technology scaling faced over the past recent decades severe variability and reliability challenges. One of the major reliability challenges is bias temperature instability (BTI). This paper analyzes the impact of BTI on the sensing delay of standard latch-type sense amplifier (SA), which is one of the critical components of high performance memories; the analysis is done by incorporating the impact of process, voltage, and temperature variations (in order to investigate the severity of the integral impact) and by considering different workloads and four technology nodes (i.e., 45, 32, 22, and 16 nm). The results show the importance of taking the SA degradation into consideration for robust memory design; the SA degradation depends on the application and technology node, and the sensing delay can increase with 184.58% for the worst case conditions at 16 nm. The results also show that the BTI impact for nominal conditions at 16 nm reaches a 12.10% delay increment. On top of that, when extrinsic conditions are considered, the degradation can reach up to 168.45% at 398 K for 16 nm.

A number of modeling approaches combining dataflow and finite-state machines (FSMs) have been proposed to capture applications that combine streaming data with finite control. FSM-based scenario-aware dataflow (FSM-SADF) is such an FSM/dataflow hybrid that occupies a sweet spot in the tradeoff between analyzability and expressiveness. However, the model suffers from compactness issues when the number of scenarios increases. This hampers its use in analysis of applications exposing high levels of data-dependent dynamics. In this paper, we address this problem by combining parameterized dataflow with finite control of FSM-SADF. We refer to the generalization as FSM-based parameterized SADF (FSM- $\pi$ SADF). We introduce the formal semantics of the model, in terms of max-plus algebra and in particular max-plus automata. Thereafter, by leveraging the existing results of FSM-SADF, we propose a worst-case performance analysis framework for FSM- $\pi$ SADF. We show that by using FSM- $\pi$ SADF and its analysis framework, one can, unlike with FSM-SADF, compactly capture streaming applications exhibiting high levels of data-dependent dynamics in presence of finite control. Furthermore, we show that for practical models our analysis typically yields tighter bounds on worst-case performance indicators such as throughput and latency than the existing techniques based on conservative FSM-SADF modeling (if such modeling can be applied at all). We evaluate our approach on a realistic case-study from the multimedia domain.

This article discusses a MATLAB-to-C vectorizing compiler that exploits custom instructions, for example, for Single Instruction Multiple Data (SIMD) processing and instructions for complex arithmetic present in Application-Specific Instruction Set Processors (ASIPs). Custom instructions are represented via specialized intrinsic functions in the generated code, and the generated code can be used as input to any C/C++ compiler supporting the target processor. Furthermore, the specialized instruction set of the target processor is described in a parameterized way using a target processor-independent architecture description approach, thus allowing the support of any processor. The compiler has been used for the generation of application code for two different ASIPs for several benchmarks. The code generated by the compiler achieves a speedup between 2× --74× and 2× --97× compared to the code generated by the MathWorks MATLAB-to-C compiler. Experimental results also prove that the compiler efficiently exploits SIMD custom instructions achieving a 3.3 factor speedup compared to cases where no SIMD processing is used. Thus the compiler can be employed to reduce the development time/effort/cost and time to market through raising the abstraction of application design in an embedded systems/system-on-chip development context.

Neuromorphic hardware platforms implement biological neurons and synapses to execute spiking neural networks (SNNs) in an energy-efficient manner. We present SpiNeMap, a design methodology to map SNNs to crossbar-based neuromorphic hardware, minimizing spike latency and energy consumption. SpiNeMap operates in two steps: SpiNeCluster and SpiNePlacer. SpiNeCluster is a heuristic-based clustering technique to partition SNNs into clusters of synapses, where intracluster local synapses are mapped within crossbars of the hardware and inter-cluster global synapses are mapped to the shared interconnect. SpiNeCluster minimizes the number of spikes on global synapses, which reduces spike congestion on the shared interconnect, improving application performance. SpiNePlacer then finds the best placement of local and global synapses on the hardware using a meta-heuristic-based approach to minimize energy consumption and spike latency. We evaluate SpiNeMap using synthetic and realistic SNNs on the DynapSE neuromorphic hardware. We show that SpiNeMap reduces average energy consumption by 45% and average spike latency by 21%, compared to state-of-the-art techniques., 14 pages, 14 images, 69 references, Accepted in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

© 2019 This paper presents an accurate technique to extensively analyze the impact of time-zero (i.e., global and local variation) and time-dependent (i.e., voltage, temperature, workload, and aging) variation on the offset voltage specification of a memory sense amplifier design using 45 nm predictive technology model (PTM) high performance library. The results show that increasing the supply voltage both for time-zero and time-dependent reduces the offset voltage specification marginally, irrespective of the process corners. In contrast, the offset voltage specification is very sensitive to the temperature and the workload, i.e., the applied voltage patterns. The results also show that a balanced workload results in a significantly lower offset voltage specification. The above results can be used to estimate the required offset voltage accurately for a given lifetime, and operational conditions such as workload, temperature, and voltage; hence, enable the designer to take appropriate measures for a high quality, robust, optimal and reliable design. ispartof: MICROELECTRONICS RELIABILITY vol:99 pages:52-61 status: published

© 2018 American Scientific Publishers. All rights reserved. Heartbeat classification using electrocardiogram (ECG) data is an essential feature of modern day wearable devices. State-of-the-art machine learning-based heartbeat classifiers are designed using convolutional neural networks (CNN). Despite their high classification accuracy, CNNs require significant computational resources and power. This makes the mapping of CNNs on resource- And power-constrained wearable devices challenging. In this paper, we propose heartbeat classification using spiking neural networks (SNN), an alternative approach based on a biologically inspired, event-driven neural networks. SNNs compute and transfer information using discrete spikes that require fewer operations and less complex hardware resources, making them energy-efficient compared to CNNs. However, due to complex error-backpropagation involving spikes, supervised learning of deep SNNs remains challenging. We propose an alternative approach to SNN-based heartbeat classification. We start with an optimized CNN implementation of the heartbeat classification task and then convert the CNN operations, such as multiply-accumulate, pooling and softmax, into spiking equivalent with a minimal loss of accuracy. We evaluate the SNN-based heartbeat classification using publicly available ECG database of the Massachusetts Institute of Technology and Beth Israel Hospital (MIT/BIH), and demonstrate a minimal loss in accuracy when compared to 85.92% accuracy of a CNN-based hearbeat classification. We demonstrate that, for every operation, the activation of SNN neurons in each layer is sparse when compared to CNN neurons, in the same layer. We also show that this sparsity increases with an increase in the number of layers of the neural network. In addition, we detail the power-accuracy trade-off of the SNN and show a 87.76% and 96.82% reduction in SNN neuron and synapse activity, respectively, for accuracy loss ranging between 0.6% and 1.00%, when compared to a CNN-only implementation. ispartof: JOURNAL OF LOW POWER ELECTRONICS vol:14 issue:4 pages:508-519 status: published

As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability-related variability) is an emerging concern that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-called defect-centric picture in terms of an ensemble of individual defects. The properties of gate oxide defects are discussed. It is further shown how in particular the electrical properties can be used to construct time-dependent variability distributions and can be propagated up to transistor-level circuits.

A paradigm for MOSFET instabilities is outlined based on gate oxide traps and the detailed understanding of their properties. A model with trap energy levels in the gate dielectric and their misalignment with the channel Fermi level is described, offering the most successful strategy to reduce both Positive and Negative Bias Temperature Instability (PBTI and NBTI) in a range of gate stacks. Trap temporal properties are determined by tunneling between the carrier reservoir and the trap itself, as well as thermal barriers related to atomic reconfiguration. Trap electrostatic impact depends on the gate voltage and its spatial position, randomized by variations in the channel potential. All internal properties of traps are distributed, resulting in distributions of the externally observable trap parameters, and in turn in time-dependent variability in devices and circuits.

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moore’s Law. For the first time, the performance of two GAA device options—lateral FET (LFET) and vertical FET (VFET)—is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi- $V_{\rm th}$ optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power.

Emerging 4G wireless communication systems need to deliver much higher data rates, more flexibility, and a significantly higher energy efficiency than current systems. To cope with this immense increase of requirements, new design approaches are a necessity. This paper focuses on the design of an advanced multiple-input–multiple-output (MIMO) detector, which is typically a bottleneck in the wireless receiver. In the proposed template-based design approach innovative architecture concepts, such as very wide register and distributed loop buffer, and algorithm-architecture co-optimizations are combined. The resulting MIMO detector processor, which is scalable to eight and more antennas, achieves a high area efficiency of 571 GOPS/ $\mathrm{mm}^{2}$ and a high energy efficiency of 3.3 GOPS/mW in the Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm technology. By exploiting the dynamically varying requirements, the proposal has the potential to achieve a higher average energy efficiency than an application-specific integrated circuit (ASIC) equivalent. However, a penalty in total area consumption exists. The proposed architecture style offers an interesting and a very promising tradeoff in between the traditional ASIC and the other programmable processor solutions.

Optimizations related to memory accesses and data storage make a significant difference to the performance and energy of a wide range of data-intensive applications. These techniques need to evolve with modern architectures supporting wide memory accesses. We investigate array interleaving , a data layout transformation technique that achieves energy efficiency by combining the storage of data elements from multiple arrays in contiguous locations, in an attempt to exploit spatial locality. The transformation reduces the number of memory accesses by loading the right set of data into vector registers, thereby minimizing redundant memory fetches. We perform a global analysis of array accesses, and account for possibly different array behavior in different loop nests that might ultimately lead to changes in data layout decisions for the same array across program regions. Our technique relies on detailed estimates of the savings due to interleaving, and also the cost of performing the actual data layout modifications. We also account for the vector register widths and the possibility of choosing the appropriate granularity for interleaving. Experiments on several benchmarks show a 6--34% reduction in memory energy due to the strategy.

Based on realistic circuit- and system-level simulations, graphene interconnects are analyzed in terms of multiple material properties, such as the mean free path (MFP), the contact resistance, and the edge roughness. The benchmarking results indicate that the advantage of using graphene interconnects occurs only under certain circumstances. The device-level parameters, including the supply and threshold voltages, and the circuit-level parameters, including the wire length and width, have large impacts on both the delay and energy-delay product (EDP). At the circuit level, one representative circuit, a 32-bit adder, is investigated, where up to 40% and 70% improvements in delay and EDP are observed. At the system-level analysis, an ARM Cortex-M0 processor is synthesized, and placement and routing are performed. After replacing copper interconnects with multilayer graphene interconnects, up to 15% and 22% performance improvements in clock frequency and EDP have been observed. It is also demonstrated that the benefits of using graphene for the ARM core processor are strongly dependent on the quality of the graphene, such as the MFP and the edge roughness.

Transient errors are a major concern for the correct operation of low-level cache memories. Aggressive integration requires effective mitigation of such errors, without extreme overheads in power, timing, or silicon area. We demonstrate a hybrid (hardware–software) scheme that mitigates bit flips in data that reside in low-level caches. The methodology is shown to be applicable in streaming applications and we illustrate that with a video decoding case study on a state-of-the-art many-core chip. The single-chip cloud computer is an experimental processor created by Intel Labs. Dedicated on-chip memories are utilized to keep safe copies for key application data, thus allowing rollbacks upon error detection. The experimental results illustrate the tradeoff between application delay, consumed energy, and output fidelity as the injected errors are corrected. When output fidelity is considered as a hard constraint, application slack used for mitigation can be reclaimed with dynamic frequency scaling. Output fidelity is guaranteed regardless of the error injection intensity and the application's timing constraints are respected up to a certain upper bound of error injection.

Bias Temperature Instability (BTI) is a major concern for the reliability of decameter to nanometer devices. Older modeling approaches fail to capture time-dependent device variability or maintain a crude view of the device's stress. Previously, a two-state atomistic model has been introduced, which is based on gate stack defect kinetics. Its complexity has been preventing seamless integration in simulations of large device inventories over typical system lifetimes. In this paper, we present an approach that alleviates this complexity. We introduce a novel signal representation for the gate stress. Using this format, atomistic BTI simulations require less model iterations while exhibiting minimum accuracy degradation. We also enable full temperature and voltage supply dependency since these attributes are far from constant in modern integrated systems. The proposed simulation methodology retains both the atomistic property and the workload memory that remain major differentiators of defect-based BTI simulation, in comparison to state-of-the-art approaches.