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This paper presents an all digital delay-locked loop (DLL) which achieves low jitter and stable duty cycle correction (DCC) operation. Since the DLL has dual DCC circuit, with the combinations of two DCC circuits, the DLL can correct +12.9% and -6.13% duty error under 2% at 333 MHz with 1.6 V. The DLL operates up to 1.67 GHz with 1.8 V and 1.78 GHz with 2.0 V supply voltage, and its peak-to-peak jitter at 1.4 GHz with 1.8 V is 29 ps. The power dissipations are 4.2 mW (5 mW) at 100 MHz and 19.8 mW (29.5 mW) at 1 GHz with 1.5 V (1.8 V) supply voltage with the help of the update gear circuit from the previous work. And the DLL is fabricated with 54-nm DRAM CMOS technology. The active area of the DLL is 0.11 mm2.

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.

This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 mum CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7 ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2.

Coverage expandable current type code controlled DCC is presented, which has TDC-based range selector. The TDC-based range selector is composed of the TDC, the anti-harmonic lock block and the encoder/decoder. The code controlled current source has asymmetric current source to both current sinks for duty error correction and is controlled by binary digital codes. And the DCC amplifier controlled by binary codes has switches which are selected according to the input frequency range. With the frequency range information, the DCC amp can expand the cover range with suitable bit resolutions. The proposed circuit is designed and simulated with 54nm CMOS technology. The DCC circuit can correct at least duty error of 6% from 500MHz through 1.25GHz.

This paper describes a 4bit parallel flash Analog-to-Digital converter (ADC) using two sub Flash ADCs and comb-type reference ladder. High speed full flash ADCs have been suffered from input referred noise which is noise itself of analog input or noise inferred from reference ladder. As power supply voltage goes lower and resolution goes higher, noise inferred from reference ladder becomes more critical to ADC's performance. The proposed ADC consists of two parallel sub-ADCs with divided reference ladder to overcome degradation due to small reference voltage step. Simulation results show that the proposed ADC achieves 3.96 effective number of bit (ENOB) for 46MHz input signal and 3.94 ENOB for 1046MHz input signal at 2GHz sampling rate. At 2GSample/s, the current consumption is 45mA including digital logic with 1.8v power supply voltage. The proposed 4bit ADC is designed with 0.18um CMOS technology.

The proposed wide-range digital duty cycle correction (DCC) circuit corrects an arbitrary input clock duty ratio to 50% while preserving the output clock phase even when the input clock duty ratio suddenly changes. Also, DCC control information is preserved during power-down mode. In this work, for input frequency range of 500MHz to 2GHz with ±10% duty ratio error, the output duty ratio error is corrected to be less than ±1.4%. The proposed DCC circuit is designed and verified using a 0.18um CMOS technology.

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces E × D by 45.5% over ep-SFF. The simulations were performed in a 0.1 μm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.

This paper describes a warpage study on LOC-TSOP memory devices. The main objectives of this study are to evaluate the impacts of epoxy mold compounds on package warpage with different sized dies. It was found that the balance of the bending between the edge side region and the die attach region controls the package warpage. The package tends to bend convex upwards in the edge side region and concave downwards in the die attach region. The various mold compounds were prepared to study the affect on the components, particularly the resin and the filler. It has been shown that the optimum mold compound can be changed according to the inner structure of the LOC-TSOP. The effect of post-mold cure on package warpage was also examined based on the cure rate.