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The increased phase number of multiphase systems enables us to exploit more degrees of freedom, such as the shape of phase carriers in pulsewidth modulation (PWM). The sawtooth carrier-based PWM (SCPWM) techniques are proposed in this article to reduce common-mode voltage (CMV) in both the peak-to-peak amplitude and the changing frequency, and it can be easily extended to symmetrical multiphase two-level inverters with any odd phase number. Theoretical analysis reveals that the switching between mirror-symmetrical carriers within one phase narrows the range of the sum of switching states in all phases, which leads to the reduction of CMV amplitude. Meanwhile, the overlapping of sawtooth carriers’ straight edges among different phases slows down the change of the sum of switching states, which results in the decrease of CMV changing frequency. Moreover, the effects of voltage harmonics injection and switches’ dead-time settings on the CMV reduction performance under the proposed SCPWM techniques are investigated. Finally, the experiment results in a five-phase induction machine and multiphase RL loads verify the improved CMV performance and the extensibility of the proposed SCPWM methods. [ABSTRACT FROM AUTHOR]

The voltage-source inverter with pulsewidth modulation (PWM) is widely used in motor drive applications owing to the technical maturity and simplicity. However, the inverter operating in the discrete and impulse state generates the high-frequency common-mode voltage (CMV) in the neutral point terminal of stator winding, which induces the negative effects. This article proposes a CMV elimination modulation scheme for the dual two-level inverter-fed asymmetrical six-phase permanent magnet synchronous motor, which has two sets of three-phase windings spatially shifted by 30° electrical degrees. The modulation algorithm shifts the PWM signals with the designed end-to-end cyclic sequence, which can retain the zero-voltage vectors for each sub-CMV of dual three-phase windings and theoretically eliminate the total CMV for the motor drive system. The validation of the proposal is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

In a motor drive system, the inverter working in discrete and impulse states generates a common-mode voltage (CMV) at the terminal of the stator winding neutral point. The high-frequency CMV can induce a leakage current and a common-mode (CM) electromagnetic interference (EMI), which are potential threats to personal safety and system stability. The conventional single three-phase inverter is found to be powerless in eliminating the CMV, while the two paralleled inverters can effectively eliminate the CMV theoretically, but the three coupled inductors (CIs) should be added to the motor drive system which reduces the power density and efficiency of the system. A novel method, which associates a specially designed dual-segment three-phase motor with the CMV elimination modulation algorithm, can be utilized to cancel the extra CIs without degrading the function of the leakage current and the CM EMI suppression. The design of the dual-segment three-phase permanent magnet synchronous machine is introduced, with identical back electromotive forces for two groups of windings but with little magnetic coupling between them. Simulation and experimental results are provided to verify the validity of the proposed method in CM-related reduction and CI cancellation. Compared with the zero-CM pulsewidth modulation for paralleled inverters proposed in a previous work, the proposed dual-segment three-phase motor drive can achieve a better power density by removing the CIs. [ABSTRACT FROM AUTHOR]

In voltage-source inverters (VSIs), dead time is used to prevent shoot-through over switching devices. However, the existence of the dead time will distort the output phase current, which degrades the performance of the inverter as well as influences the common-mode voltage (CMV), particularly in CMV elimination relevant modulation schemes, such as zero-common-mode (CM) pulsewidth modulation (PWM)-based paralleled inverters. In the light of the situation that the normal sampling-based dead-time compensation (DTC) methods are often disturbed by the current ripple, this paper introduces a novel DTC method for the VSI, which can mitigate the impact of the current ripple and improve the accuracy of DTC. The proposed method deduces the real-time current ripple, which can reconstruct the actual trajectory of phase-leg currents, and the peak values corresponding to rising and falling edges for PWM signals can be predicted. In this way, DTC can be implemented based on the direction of relevant instantaneous switching currents and finally improves the accuracy. Especially, the current-ripple-prediction-based DTC can help to improve the CMV distortion caused by the dead time for paralleled inverters with zero-CM PWM. Simulation and experimental results are provided to validate that the proposed method can be applied to different topologies and modulation schemes with good performance. [ABSTRACT FROM AUTHOR]