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This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage (V t h) and gate leakage current (I g s s) in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in S i O 2 caused by oxide electric field (E o x)  stress affect the V t h of SiC MOSFETs. The saturation and turnaround behavior of the V t h shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The I g s s under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of V t h shift and I g s s under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests. [ABSTRACT FROM AUTHOR]

This paper discusses the design methodologies and fabrication of a 4H-SiC lateral reduced surface electric field (RESURF) Schottky barrier diode (SBD), using a very thin (0.7 μm) RESURF layer. The proposed optimization of the anode and cathode edge structure with recessed etch into mesa termination minimizes the electric field induced impact ionization at the edge of the active area. Three-dimensional simulations were conducted to optimize electric field distribution and enable close to ideal RESURF breakdown voltage within the device, while enabling junction isolation structure between neighboring devices through mesa etch. The design methodologies and the fabricated lateral SBD offer guidance for future efforts toward realizing a monolithic SiC high voltage integrated circuit. [ABSTRACT FROM AUTHOR]