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The undoped 4-stacked Ge0.9Sn0.1 nanosheets sandwiched by double Ge0.95Sn0.05 caps without parasitic Ge channels underneath are realized by a radical-based highly selective isotropic dry etching. Highly inter-channel uniformity of the stacked GeSn nanosheets is realized by thin Ge0.9Sn0.1 (5 nm) channels and thick Ge0.95Sn0.05 caps to achieve high $\mathrm{I}_{\mathrm{\scriptscriptstyle ON}}$ . The caps are the barriers to separate the holes from the dielectrics/cap interface to reduce the surface roughness scattering. The double caps with small strain also stabilize the channels to prevent the channel buckling. The undoped GeSn nanosheets with [B] below the detection limit ( $ cm $^{-{3}}$ ) and heavily doped ( $\sim {2} \times {10}^{{21}}$ cm $^{-{3}}$ ) Ge at S/D can suppress the impurity scattering to increase the channel mobility and can reduce the S/D resistance, respectively. The high ${I}_{{\mathrm{\scriptscriptstyle ON}}} = {73}\,\,\mu \text{A}$ per stack (86 $\mu \text{A}/\mu \text{m}$ , normalized by the total perimeter of nanosheets) at ${V}_{\text {OV}} = {V}_{\text {DS}} = - {0.5}$ V is achieved for the device with the sheet width of 80 nm and the Lg of 80 nm. The quantum mechanical simulation shows that there is heavy hole population at the two ends of nanosheets.

The undoped 4-stacked Ge 0.9 Sn 0.1 nanosheets sandwiched by double Ge 0.95 Sn 0.05 caps without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. High inter-channel uniformity of the stacked GeSn nanosheets is achieved to enhance ION by thin Ge 0.9 Sn 0.1 (5nm) channels. The carriers are separated from dielectrics by the caps to reduce the impurity and surface roughness scattering. The double caps with small strain also stabilize the channels to prevent the channel buckling. The undoped GeSn nanosheets with [B] below the detection limit ( ON =73μA per stack (910μA/μm per channel footprint) at V OV =V DS =-0.5V is achieved among GeSn 3D FETs for the sheet width/Lg of 80nm/80nm. The I ON per channel footprint can be improved to 1070μA/μm with the sheet width scaled to 57nm due to the large carrier population at the two ends of nanosheets. The double caps as barriers for the holes in the Ge 0.9 Sn 0.1 nanosheets decrease the low frequency noise by reducing trapping/detrapping between the GeSn nanosheets and the gate dielectrics.

The undoped stacked GeSn channels without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. Heavily doped Ge sacrificial layers can reduce S/D resistance and the undoped GeSn channels can increase the channel mobility. SS=89m V /dec and $\mathrm{I}_{\mathrm{O}\mathrm{N}}=42\mu 1$ per stack ( $10.5\mu A$ . per sheet) at $\mathrm{V}_{\mathrm{OV}}\mathrm{V}_{\mathrm{DS}}=-0.5\mathrm{V}$ are achieved for the undoped 4-stacked 12nm-thick nanosheets with 120nm gate length and the width larger than 50nm. The etching selectivity and the channel uniformity are highly improved by the dry etching as compared to H202 wet etching. Both dry etching and undoped channel are essential to obtain stacked wide nanosheets with high performance.

Si incorporation as small as 2% into Ge can achieve sufficient etching selectivity of heavily phosphorus- doped Ge sacrificial layers over unintentionally doped Ge 0.98 Si 0.02 to form two stacked Ge 0.98 Si 0.02 nanowire channels, and introduce 0.27% uniaxial tensile strain for the electron mobility enhancement. The alloy scattering is still minimal for 2% Si. The parasitic Ge/Si channel underneath the Ge 0.98 Si 0.02 channels is completely removed by optimized etching. The infrared response of the parasitic channel is a non-destructive method to further confirm the removal of the parasitic channel. VT can be tuned by PMA, and ION can be enhanced by short L G . Record ION of 48 μA at V OV =V DS =0.5V and record Q (G m,max/ SS SAT ) of 8.3 at V DS =0.5V with L G = 40 nm are achieved among Ge nFETs. The results are comparable to Si nFETs.

Record [Sn]=12% and record compressive strain of 3.3% among GeSn 3D transistors to enhance the ION are demonstrated by CVD epitaxy. For the first time, in-situ Ge 0.95 Sn 0.05 caps are grown on stacked Ge0.ssSn0.12 channels to improve interface quality and separate carriers from the interface to achieve high mobility. L G is scaled down to 40nm to further boost the ION. Low channel doping and high S/D doping ([B] peak ~1E21cm-3) can suppress the impurity scattering in the channels and reduce the contact resistivity for the S/D, respectively, to reveal the intrinsic merit of the high mobility of GeSn. The stacked 3 Ge 0.88 Sn 0.12 nanosheets achieve record ION of 58µA at V OV =V DS = -0.5V and record G m,max of 172µS at V DS = -0.5V among GeSn pFETs, and the performance is comparable to mature Si FinFETs, stacked Si channels, and stacked Ge channels. The caps as barriers on the Ge0.ssSn0.12 channels decrease the low frequency noise by reducing trapping/detrapping between the GeSn channels and the gate dielectrics.