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Equivalent‐time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down‐conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in‐phase/quadrature gain imbalance instead of requiring a high‐speed analog‐to‐digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent‐time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent‐time sampling using DDC. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter–amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta–sigma modulator was designed and fabricated in a 0.18 μm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively. [ABSTRACT FROM AUTHOR]

The sigma-delta modulator (SDM) is one of the well-established data converter architectures. It is well-known for achieving a high signal-to-noise ratio (SNR). In the SDM, the integrators in the loop filter could suffer from overloading if the signal swing exceeds its maximum level, which leads to performance and SNR degradation. Thus, scaling the system coefficients is needed, such that there is no overloading for the integrators. In this work, we present a systematic general method that could be used for scaling the signal swings in the continuous-time low-pass sigma-delta modulator (SDM). The proposed method can be applied to any continuous-time low-pass SDM architecture, and it includes the scaling of all the possible combinations of the system coefficients. Moreover, an open-source Simulink-based toolbox that includes the systematic method is presented. This toolbox could help the designer to execute the scaling process and the simulations in an efficient way. In addition to that, a design example is discussed to illustrate the proposed method, wherein the presented toolbox is used for simulations, and the simulation results are shown. [ABSTRACT FROM AUTHOR]

This paper presents a new self-clocked time-to-digital conversion method based on a binary successive approximation (SA) algorithm. Its novelty consists in combining fully clockless operation with direct conversion of the measured time interval. The lack of any reference clock makes the presented method potentially predisposed to low-power solutions. Furthermore, its circuit representation is extremely simple, thereby the ability to direct conversion of time intervals is not burdened by a significant amount of components. The method is intended to measure relatively long time intervals, i.e., hundreds of microseconds. Therefore, it is suitable for e.g., biomedical applications using time-mode signal processing. [ABSTRACT FROM AUTHOR]

This research paper delves into a comprehensive investigation concerning the impact of additive noise and quantization error on the precision of amplitude, offset, and phase estimates of a sine wave fitted to a set of data points acquired by a waveform digitizer. Simulation results are used to validate the expressions presented. [ABSTRACT FROM AUTHOR]

This paper reviews the state of the art on bandpass Σ Δ modulators (BP- Σ Δ Ms) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP- Σ Δ M analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efficient and feasible to be embedded in mobile terminals. [ABSTRACT FROM AUTHOR]

This article presents a 5-GS/s continuous-time (CT) multi-stage noise-shaping (MASH) analog-to-digital converter (ADC). The ADC consists of three first-order modulators with a 3-bit quantizer/digital-to-analog converter (DAC) per stage. An RC-hybrid stabilization DAC is used to compensate for the excess loop delay and excess phase shift. A delay matching all-pass input filter with a low-pass feedforward filter is employed to suppress input signal leakage. As a result, inter-stage DACs are waived in residue generation, and low-power, area-saving Gm-C integrators are enabled in the back-end stages. The MASH ADC was implemented in 40-nm CMOS and occupies 0.21 mm2. The ADC achieves 68-dB dynamic range (DR) and 65-dB signal-to-noise and distortion ratio (SNDR) over a 360-MHz bandwidth (BW). The ADC consumes 158 mW from 1/1.1/1.8 V supplies, yielding 159-dB Schreier figure-of-merit (FOM) and 151-fJ/Conv. Walden FOM. [ABSTRACT FROM AUTHOR]

Wearable sensors have demonstrated wide applications from medical treatment, health monitoring to real-time tracking, human-machine interface, smart home, and motion capture because of the capability of in situ and online monitoring. Data acquisition is extremely important for wearable sensors, including modules of probes, signal conditioning, and analog-to-digital conversion. However, signal conditioning, analog-to-digital conversion, and data transmission have received less attention than probes, especially flexible sensing materials, in research on wearable sensors. Here, as a supplement, this paper systematically reviews the recent progress of characteristics, applications, and optimizations of transistor amplifiers and typical filters in signal conditioning, and mainstream analog-to-digital conversion strategies. Moreover, possible research directions on the data acquisition of wearable sensors are discussed at the end of the paper. [ABSTRACT FROM AUTHOR]

Determining the quality of sensing devices exhibiting minimal digitization complexity is addressed. Measurements of such sensor systems are characterized by multivariate binary distributions and assessing sensitivity via the Cramér-Rao lower bound turns out to be intractable. In this context, the Fisher matrix of the exponential family and a lower bound for arbitrary probabilistic models are discussed. The conservative approximation for Fisher’s information matrix rests on a surrogate exponential family distribution connected to the actual data-generating system by two compact equivalences. Without characterizing the likelihood and its support, this probabilistic notion enables designing estimators that consistently achieve the sensitivity level defined by the inverse of the conservative information matrix. For hard-limited multivariate Gaussian signal models, a quadratic exponential surrogate distribution tames statistical complexity such that a quantitative and conservative assessment of Fisher information becomes possible. This result is exploited for the Fisherian quantization loss analysis of an array with low-complexity binary sensors in comparison to an ideal system featuring infinite amplitude resolution. Additionally, data-driven assessment by estimating a conservative approximation for the Fisher matrix under recursive binary sampling as implemented in ΣΔ-modulating analog-to-digital converters is demonstrated. [ABSTRACT FROM AUTHOR]

A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. A reference-embedding flash ADC for a fine stage having only a single capacitive digital-to-analog converter improves the power efficiency and area efficiency as well as the input bandwidth. The proposed sample-and-hold sharing structure not only improves the input bandwidth by removing the effect of the input capacitance of the fine ADC (FADC) but also eliminates the gain error between the coarse ADC and the FADC. The advanced sequential slope-matching offset calibration technique in the eight-time interpolated FADC improves the gain of the voltage-to-time converter and the interpolation linearity. A prototype ADC implemented in a 40-nm CMOS process occupies 0.03 mm2, including offset calibration circuitry. The measured peak differential non-linearity (DNL) and integral non-linearity (INL) after calibration are 0.53 and 0.47 LSB, respectively. With a 1.49-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.94 and 55.78 dB, respectively. The ERBW without and with time skew calibration is 4.8 and 7 GHz, respectively. The power consumption is 6.8 mW under a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 28 fJ/conversion-step at 3 GS/s. [ABSTRACT FROM AUTHOR]

This article presents a single-channel 3.3-GS/s 6-b pipelined analog-to-digital converter (ADC), which features a post-amplification residue generation (PARG) scheme, linearized dynamic amplifier (DA), and on-chip calibration to achieve a high speed, low power, and compact prototype. The PARG scheme allows the quantization and amplification to run in parallel for a fast pipelining operation. The 6-b ADC consists of six pipelined stages with six comparators and five amplifiers in total. Such a small number of hardware reduce the overhead from the calibration and enable fully on-chip implementation. By further sharing the calibration hardware between the offset and gain calibration, the ADC with on-chip calibration only occupies 0.0166 mm2 in 28-nm CMOS. With a linearized DA for the residue amplification, the ADC achieves 34-dB signal-to-noise and distortion ratio (SNDR) with a Nyquist input with 3.3 GS/s, consuming 5.5 mW and yielding a 40.02-fJ/conversion-step Walden figure of merit (FoM). [ABSTRACT FROM AUTHOR]

A control-bounded analog-to-digital converter consists of a linear analog system that is subject to digital control, and a digital filter that estimates the analog input signal from the digital control signals. Such converters have many commonalities with delta–sigma converters, but they can use more general analog filters. The paper describes the operating principle, gives a transfer function analysis, and describes the digital filtering. In addition, the paper discusses two examples of such architectures. The first example is a cascade structure reminiscent of, but simpler than, a high-order MASH converter. The second example combines two attractive properties that have so far been considered incompatible. Its nominal conversion noise (assuming ideal components) essentially equals that of the first example. However, its analog filter is a fully connected network to which the input signal is fed in parallel, which potentially makes it more robust against nonidealities. [ABSTRACT FROM AUTHOR]

Mismatches between sub-channels limit the dynamic performance of time-interleaved analog-to-digital converters (TI-ADCs). This paper proposes a correlation-based method of calibration for timing mismatches in M-channel TI-ADCs by using the cross-correlation between sub-channels of the output signals to estimate the temporal deviations. The output signal is calibrated by reducing the arbitrary order distortion, which is approximated by multiplying the distortions with the estimated coefficients of mismatch. Furthermore, a reconfigurable strategy composed of stages of arbitrary calibration is proposed to achieve suitable stages with the requisite dynamic performance. Finally, the calibration performance of the proposed method is verified through simulations that use different input signals and strengths of mismatch. [ABSTRACT FROM AUTHOR]

A study of methods for correcting amplitude and phase errors in devices for measuring the parameters of electric power with digital signal processing with a sampling frequency multiple of the network frequency was made. The generalized flow diagram of measuring device that consists of a few entrance channels was presented. Mathematical expositions that explain the process of correction of additive and multiplicative errors are given. Through a temporal diagram a few variants of encoding of entrance signals are shown. The possibility of correcting phase errors by shifting the moment of the ADC start-up and by turning the axes and transforming the coordinates of the voltage and current vectors is shown. The possibility of correction when measuring the reactive and reactive powers is investigated. [ABSTRACT FROM AUTHOR]

A second-order multi-bit Σ Δ modulator facilitating the usage of a two-step flash analog-to-digital converter (ADC) as an internal quantizer is presented. A digital assisted low-resolution feedback digital-to-analog converter (DAC) is introduced containing digital sigma-delta modulators (DSDMs) to reduce the number of levels in the feedback DAC alleviating dynamic element matching requirements. Two-step flash ADC as an internal quantizer in a Σ Δ modulator provides higher resolution; however, the delay in the two-step ADC can introduce instability in the Σ Δ modulator loop. In the proposed architecture, the fast processing of the digital integrator of DSDM in the feedback path compensates the latency of the two-step flash ADC. Therefore, this architecture provides more than 6 bits of resolution in the internal quantizer. The implementation of an extra DSDM in the outermost feedback path relaxes the matching requirement of the analog and digital integrators. The effectiveness of the proposed structure is demonstrated by the study of nonlinearities of the analog integrators. [ABSTRACT FROM AUTHOR]

A novel digital adaptive blind calibration technique for frequency-interleaved analog-to-digital converters (FI-ADCs) with arbitrary numbers of channels is proposed. It performs the estimation and correction of multiple inherent circuit deficiencies alternately and recursively in the background, including spectral leakage, harmonic folding, jitter, I/Q mirror and aliasing images, and suffices to deliver projected calibration capabilities with deliberately chosen initial guesses. We are of the opinion that this is the first study to address the joint channel identification and error compensation problem encountered in the FI-ADC design. For the efficient implementation, an analytical time-interleaving-like equivalent model is formulated such that the number of unknown mismatch parameters is significantly reduced, and signals devoted to cyclic estimation are maximally decimated. This derived model not only propounds a better perspective for comprehension and interpretation of the FI system mechanism but also enables sufficient scalability and flexibility of the developed calibration framework. Extensive simulation results further show that this novel architecture achieves a good balance between the computational complexity and convergence, and provides an exceptional and relatively flat effective number of bit (ENOB) performance over a wide bandwidth. [ABSTRACT FROM AUTHOR]

This article reports a high-linearity dynamic amplifier with a gain control technique for pipelined analog-to-digital converters (ADCs). The wide input range and dynamic operation of the amplifier allow the ADC energy-efficient pipeline process. The voltage gain is controlled in the analog domain with digital gain correction codes, enabling simple compensation for process, voltage, and temperature variations. The proposed switching technique for the amplifier also defines a stable common-mode output without any dedicated hardware. An 11-bit 100-MS/s fully dynamic pipelined ADC using the open-loop dynamic amplifier is implemented without gain-linearity calibration. An ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.05 mm2, and the performances are measured at sampling rates in the range of 10–100 MHz. This ADC achieves a signal-to-noise and distortion ratio of 62 dB and a spurious-free dynamic range of 77 dB while consuming 1.33 mW of power at 100 MS/s. A Walden figure of merit of 10.8–13.1 fJ/conversion-step is achieved. [ABSTRACT FROM AUTHOR]

A 256-channel readout application specific integrated circuit (ASIC) called the very low-noise analog sampling engine (VASE) intended for the readout of column-parallel charge-coupled devices (CP-CCDs), is presented. Each channel uses a charge-sensitive amplifier and a first-order dual-gain sigma-delta analog-to-digital converter (ADC) that act as the front end of an extended counting ADC. The extended counting ADC directly implements correlated multiple-sampling as part of its operation. To reduce the noise due to input capacitance and to ensure a compact camera, the VASE input bonding pads are pitch matched to the CP-CCD to allow chip-to-chip bonding with minimal parasitic capacitance. The chip is designed in a modular way with each 16 input channels sharing a single differential analog output and digital serializer. VASE, with a die area of 38.1 mm2 and fabricated in 180-nm CMOS technology, achieves 22 e− equivalent noise charge (ENC) and a dynamic range of 190 ke− (78.7 dB) at a 4-MHz pixel rate (corresponding to a frame rate of 32 kfps when a 256×256 pixel sensor is read out on both sides) while dissipating 10.1 mW per channel. The prototype has been used to successfully image X-ray diffraction at a soft X-ray synchrotron. [ABSTRACT FROM AUTHOR]

We investigate time encoding as an alternative method to classical sampling, and address the problem of reconstructing classes of non-bandlimited signals from time-based samples. We consider a sampling mechanism based on first filtering the input, before obtaining the timing information using a time encoding machine. Within this framework, we show that sampling by timing is equivalent to a non-uniform sampling problem, where the reconstruction of the input depends on the characteristics of the filter and on its non-uniform shifts. The classes of filters we focus on are exponential and polynomial splines, and we show that their fundamental properties are locally preserved in the context of non-uniform sampling. Leveraging these properties, we then derive sufficient conditions and propose novel algorithms for perfect reconstruction of classes of non-bandlimited signals such as: streams of Diracs, sequences of pulses and piecewise constant signals. Next, we extend these methods to operate with arbitrary filters, and also present simulation results on synthetic noisy data. [ABSTRACT FROM AUTHOR]

Quantization plays a critical role in digital signal processing systems. Quantizers are typically designed to obtain an accurate digital representation of the input signal, operating independently of the system task, and are commonly implemented using serial scalar analog-to-digital converters (ADCs). In this work, we study hardware-limited task-based quantization, where a system utilizing a serial scalar ADC is designed to provide a suitable representation in order to allow the recovery of a parameter vector underlying the input signal. We propose hardware-limited task-based quantization systems for a fixed and finite quantization resolution, and characterize their achievable distortion. We then apply the analysis to the practical setups of channel estimation and eigen-spectrum recovery from quantized measurements. Our results illustrate that properly designed hardware-limited systems can approach the optimal performance achievable with vector quantizers, and that by taking the underlying task into account, the quantization error can be made negligible with a relatively small number of bits. [ABSTRACT FROM AUTHOR]

Analog-to-digital (A/D) converters are the common interface between analog signals and the domain of digital discrete-time signal processing. In essence, this domain simultaneously incorporates quantization both in amplitude and time, i.e. amplitude quantization and uniform time sampling. Thus, we view A/D conversion as a sampling process in both the time and amplitude domains based on the observation that the underlying continuous-time signals representing digital sequences can be sampled in a lattice—i.e. at points restricted to lie on a uniform grid both in time and amplitude. We refer to them as lattice functions. This is in contrast with the traditional approach based on the classical sampling theorem and quantization error analysis. The latter has been mainly addressed with the help of probabilistic models, or deterministic ones either confined to very particular scenarios or considering worst-case assumptions. In this paper, we provide a deterministic theoretical analysis and framework for the functions involved in digital discrete-time processing. We show that lattice functions possess a rich analytic structure in the context of integral-valued entire functions of exponential type. We derive set and spectral properties of this class of functions. This allows us to prove in a deterministic way and for general bandlimited functions a fundamental lower bound on the maximum frequency component introduced by quantization that is independent of the resolution of the quantizer. [ABSTRACT FROM AUTHOR]

In cognitive radio (CR) networks, the role of spectrum sensing (SS) is crucial to enable an efficient exploitation of the radio spectrum resource. The need to measure spectrum occupancy turns CRs to be de facto measurement instruments, so it becomes crucial to analyze how real instrumentation peculiarities could affect performance in spectral measurements (i.e., SS performance). In this paper, a commercial software-defined radio (SDR) is adopted as cognitive device, and its capability to accurately measure occupied spectrum is analyzed in comparison also with a simulation setup, where the same analog-to-digital converter (ADC) is modeled and simulated, and equivalent signal-to-noise ratios (SNRs) are replicated. To this aim, a suitable experimental setup has been designed, metrologically characterized, and tuned. Experimental results prove how nominal SNR typically adopted for testing the performance of SS methods is not sufficient to model the impairments of a real acquisition chain, even jointly with a modeling of the digitization process. To assure a reliable SS method validation, new approaches have to be considered for enhancing the accordance between the performance predicted in the simulation environment and the experimental one reachable on real devices. Since different architectures of CRs are present on the market, the experimental tests should be preferred for a reliable SS performance assessment. [ABSTRACT FROM AUTHOR]

Serial link receivers with high-speed analog-to-digital converters (ADCs) can utilize powerful digital-domain equalizers and support multilevel modulation schemes. This paper presents a hybrid statistical modeling framework for ADC-based serial link receivers. The framework builds upon the existing statistical modeling techniques for mixed-signal receivers and adds the support of ADC quantization noise, radix errors [integral nonlinearity and differential nonlinearity (INL/DNL)], and time-interleaving mismatches. A rapid purely statistical simulation mode is utilized to model systems with small front-end nonlinearity and ADC INL/DNL. To include ADC INL/DNL, a hybrid approach is presented with an initial short transient simulation. The presented modeling framework is used to explore the effectiveness of embedding an analog feed-forward equalizer (FFE) in the ADC of a 10-Gb/s receiver. Measurement results of a 10-Gb/s ADC-based receiver prototype with a three-tap embedded FFE in the ADC and a digital four-tap FFE and three-tap decision feedback equalizer are presented to validate the presented framework. [ABSTRACT FROM AUTHOR]

This paper presents an on-chip stepwise ramp stimulus generator aimed at static linearity test applications for analog-to-digital converters (ADCs). The proposed ramp stimulus generator is based on a simple switched-capacitor integrator with a constant dc input. The integrator has been conveniently modified to produce a very small integration gain proportional to the capacitance difference of two capacitors, in such a way that the resulting stepwise ramp signal at the output has a step size below the least significant bit (LSB) of the target ADC under test. In order to verify the feasibility of the proposed ramp generation technique, this paper details the design and experimental characterization of a proof-of-concept stepwise ramp generator in a 65-nm CMOS technology. Experimental results on 15 fabricated samples show an average linearity of 14.5 effective bits in a differential output range of ±2 V. Moreover, a discrete-time static linearity measurement strategy is proposed and, as a proof-of-concept validation, it is verified on an off-the-shelf 11-bit ADC using the fabricated generator samples. Experimental results show an accuracy of ±0.3 LSB in the measurement of the integral nonlinearity of the ADC under test. [ABSTRACT FROM AUTHOR]

The main technical indicators of A/D converter were analyzed and studied with an example from A/D converter TLC2543 which is controlled by using SCM. It was completed the construction of the A/D converter circuit under the Proteus software. The programming based on the operation sequence of the chip is put forward. With the aid of the simulation tools such as virtual instrument, simulation charts provided by Proteus, the important parameters of circuit such as offset error, gain error, differential nonlinearity (DNL), integral nonlinearity (INL) and conversion time are analyzed detailedly. Simulation results show that the A/D conversion process can be qualitatively analyzed and visualized the abstract indicators of A/D. The system can help students better to understand the SCM conversion process. [ABSTRACT FROM AUTHOR]

A new technique to mitigate the non-linearity of the ring oscillator is introduced and described for open loop ring oscillator based analog-to-digital conversion. The idea is based on limiting the input signal amplitude to make the ring oscillator work in a more linear range, thus improving the SNDR p e a k. The dynamic range is preserved by means of several parallel digitization channels injected in phase. Passive interpolation between the channels is exploited to ensure a uniform distribution of the output phases. The idea is validated through system and schematic simulations using a 65 nm CMOS technology node, towards high bandwidth applications such as new communication protocols or Internet-of-Things environments. A SNDR of 63 dB is achieved with four digitization parallel channels with an input signal swing of differential 600 mV p p in a bandwidth of 50 MHz. PVT variations and mismatch effects are checked and no degradation in the final resolution is observed. Therefore, the proposal shows a high robustness without requiring any type of calibration. Additionally it is proven that the architecture consumes less than half of the power consumed by the conventional approach, leading to a higher power efficiency. [Display omitted] • Non-linearity compensation in ring oscillators-based analog-to-digital conversion by input signal attenuation without compromising the dynamic range of the data converter. • Several parallel digitization paths with uniform distribution of the ring oscillator phases by means of passive phase interpolation. • Excellent performance achieved compared to equivalent works, achieving a SNDR of 63 dB for an input swing of 600 mVpp in a pseudo-differential configuration over 50 MHz of bandwidth. • Great robustness against PVT variations and mismatch effects with no need of any calibration technique. • Better power efficiency leading to power savings higher than 50%. [ABSTRACT FROM AUTHOR]

The most recent digitizers available on the market can grant real-time bandwidth up to 70 GHz and beyond. Such a performance is achieved by transforming the signal at the analog front-end in order to produce two or more instances characterized by reduced bandwidth; the different instances are acquired by means of less demanding ADCs and combined to regain a digital representation of the input signal over the original bandwidth. Also, these digitizers use massive digital signal processing to perform the necessary calibration. However, the specific implementations that make calibration and reconstruction possible are carefully kept secret by the manufacturers. Here a proposal for streamline calibration and reconstruction of an ATI-based digitizer is illustrated and validated. [ABSTRACT FROM AUTHOR]

Hardware reconfigurability is an attractive solution for modern multi-standard wireless systems. This paper analyses the performance and implementation of an efficient triple-mode hexa-standard reconfigurable sigma-delta (∑∆) modulator designed for six different wireless communication standards. Enhanced noise-shaping characteristics and increased digitisation rate, obtained by time-interleaved cross-coupling of ∑∆ paths, have been utilised for the modulator design. Power/hardware efficiency and the capability to acclimate the requirements of wide hexa-standard specifications are achieved by introducing an advanced noise-shaping structure, the dual-extended architecture. Simulation results of the proposed architecture using Hspice shows that the proposed modulator obtains a peak signal-to-noise ratio of 83.4/80.2/67.8/61.5/60.8/51.03 dB for hexa-standards, i.e. GSM​​​​​​​​/Bluetooth/GPS/WCDMA/WLAN/WiMAX standards with significantly less hardware and low operating frequency. The proposed architecture is implemented in 45 nm CMOS process using a 1 V supply and 0.7 V input range with a power consumption of 1.93 mW. Both architectural- and transistor-level simulation results prove the effectiveness and feasibility of this architecture to accomplish multi-standard cellular communication characteristics. [ABSTRACT FROM PUBLISHER]

A 2–2 cascaded switched-capacitor $\Sigma \Delta $ modulator is presented for design of low-voltage, low-power, broadband analog-to-digital conversion. To reduce power dissipation in both analog and digital circuits and ensure low-voltage operation, a half-sample delayed-input feedforward architecture is employed in combination with 4-bit quantization, which results in reduced integrator output swings and relaxed timing constraint in the feedback path. The integrator power is further reduced by sharing an op amp in the two integrators in each stage and periodically changing the op amp bias condition between a high-current and a low-current mode using a fast low-power high-precision charge pump circuit. Implemented in a 0.18- \mu \text{m} CMOS technology, the experimental prototype achieves a 92-dB dynamic range, a 91-dB peak signal-to-noise ratio, and an 84-dB peak signal-to-noise plus distortion ratio, respectively for a signal bandwidth of 1.25 MHz. Operated at a 40-MHz sampling rate, the modulator dissipates 24.3 mW from a 1 V supply. [ABSTRACT FROM PUBLISHER]

In sensor applications, low-power and moderate-high resolution analog-to-digital converters (ADCs) are needed to convert the analog front-end signal output. Such systems are often multi-channel and require analog multiplexing. In these cases, even when high resolutions are required, continuous time $$\varDelta \varSigma $$ ADCs can't be adopted, and an efficient data-conversion must be achieved relying on different topologies, typically successive approximation-register (SAR) ADCs. Since these systems are often implemented in CMOS processes like 250- and 350-nm CMOS to benefit from a large supply voltage, the SAR ADC design is challenging due to the technology mismatch and to the limited number of metals available to optimize the layout. This paper presents a SAR ADC implemented in 350-nm CMOS technology with a physical resolution of 14 bits using a binary weighted with attenuation capacitor array. The proposed converter exploits a semi-custom and isotropic unit capacitance with ground shield to avoid proximity effects and parasitic capacitances across its terminals, an optimized capacitive array layout insensitive to both linear and radial oxide gradients, and an efficient calibration algorithm to compensate the parasitic capacitances that worsen the converter linearity. At 1.8-V supply and 100-kSps sampling frequency, the proposed ADC achieves an SNDR of 70.7 dB, an SFDR of 81.8 dB, an ENoB of 11.45 and a power consumption of $$43.4\,\upmu \hbox {W}$$ , corresponding to a figure-of-merit (FoM) of 155 fJ/conv.step. To the best of our knowledge, this figure is the best among SAR converters implemented in 350-nm or less scaled technologies, and in-line with other ADCs featuring an SNDR larger than 70 dB. [ABSTRACT FROM AUTHOR]

This paper presents a fully digital quantization noise reduction algorithm (DQNRA) for \mathrm CT\Sigma \Delta \mathrm M . The algorithm overcomes the signal leakage issues commonly found in cascade and MASH implementations. The proposed DQNRA is robust to PVT variations. The DQNRA performs a foreground measurement of the modulators noise transfer function. A \Sigma \Delta \mathrm M using a 7 bit quantizer, from which the four most significant bits are used for the operation of the \Sigma \Delta \mathrm M , proves the DQNRA concept. The remaining three least significant bits are used for the realization of the DQNRA for quantization noise improvement. A 7 bit quantizer with a three-step subranging architecture is implemented to reduce power and area consumption. A fourth-order continuous-time $\Sigma \Delta $ prototype was implemented in 130 nm CMOS technology. The modulator’s total power consumption is 20 mW, with only 6 mW used for the realization of the 7 bit quantizer operating at 500 MHz. For this prototype, the use of a DQNRA algorithm improved the modulator’s SNDR from 69 to 75 dB over a 15 MHz bandwidth, limited after calibration by thermal noise rather than quantization noise. The obtained FoM is 164 dB. [ABSTRACT FROM PUBLISHER]

This paper presents a $4 \times $ time-interleaved 6-bit 5 GS/s 3 b/cycle SAR analog-to-digital converter (ADC). Hardware overhead induced by a 3 b/cycle architecture is eased by an interpolation technique where around 1/3 of the hardware is saved. In addition, complicated switching controls are simplified with a proposed fractional DAC array switching scheme, thus reducing the design complexity and the hardware burden. A boundary detection code overriding (BDCO) is introduced to reduce error probability at the large error magnitude, by utilizing the extended time when the comparator is at reset and the DAC at settling. The floorplan of the front-end is optimized for important interleaving clock distributions, and a master-clock-control bootstrapped-switch technique is adopted to suppress the timing-skew effect among the channels. The unit capacitor has been designed to suit for the DAC structure which allows top-plate sharing in both directions, plus, the offset is calibrated on-chip with a clocking variable biasing transistor pair at the latch. Measurement results show that the prototype can achieve 5 GS/s with a total power consumption of 5.5 mW at 1 V supply in 65 nm CMOS technology. Besides, it exhibits a 30.76 dB SNDR and 43.12 dB SFDR at Nyquist, which yields a Walden FoM of 39 fJ/conversion-step. [ABSTRACT FROM PUBLISHER]

A strain measuring station for the dynamic testing of dampers is described. The mechanical stresses are measured using strain-resistive sensors, connected in a measuring Wheatstone bridge circuit. A justification for the choice of the electronic components is presented and practical recommendations are made for the development of similar devices. [ABSTRACT FROM AUTHOR]

This paper presents a 10 bit charge redistribution successive approximation analog-to-digital converter (ADC) for integrated digitally controlled DC-DC converters. A timing efficient implementation of a window function is proposed, where only a reduced input range is converted. A redundant search is applied to overcome the speed limitation of the analog components. The window mode enables further speed enhancement without an increase of clock frequency and power consumption. Position of the set-point and size of the window is digitally adjustable every conversion. Fabricated in 28 nm low-power CMOS technology the ADC occupies only 110 × 85 µm. In full range mode a conversion rate of 16 MS/s is achieved and in window mode 26.7 MS/s, respectively. With a measured total power consumption of 710 µW and 9.1 bit ENOB a FOM of 81 fJ/conv-step is reached. A large input range with constant resolution, highly linear characteristic, and high robustness to PVT variations together make this ADC an advantageous alternative to delay line or ring oscillator based window ADCs. The highly digital nature of the proposed architecture allows implementation in modern sub-100 nm CMOS technologies. [ABSTRACT FROM AUTHOR]

We optimize a proposed multicast parametric synchronous sampling scheme. Two segments of 1 cm high nonlinear spiral photonic crystal fiber are utilized as a nonlinear medium in parametric processors. Meanwhile, a segment of 1.8 km dispersion compensation fiber is used to obtain linear chirped sampling pulses instead of a 5 km single-mode fiber. The experimental results show that a 120 GSa/s equivalent sampling rate, high power of sampling copies, and low variance are obtained. [ABSTRACT FROM AUTHOR]

It is difficult to use a single analog-to-digital conversion (ADC) to satisfy the requirements for conversion of an ultra-wideband signal. A parallel architecture for wideband ADC, named cosine modulated hybrid filter bank, is presented to address this problem. First, the proposed architecture shifts the input signal spectrum by means of mixers. The modulated signal is channelized into smaller frequency subband signals using identical lowpass analog filters. Then the subband signals are digitized through identical narrowband ADCs, respectively. Finally, the digitized signals are up-sampled, filtered and combined to reconstruct the digital representation of original wide-band input signal. The digital filters are designed to the eigenfilter method based on total least squares error criterion. Since the sample-and-hold circuits needed in this architecture are simple identical narrowband baseband circuits, which makes the design easier and cheaper. Several design examples are presented to illustrate the performance of the proposed system. [ABSTRACT FROM AUTHOR]

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope. [ABSTRACT FROM AUTHOR]

Highlights: [•] The retina of vertebrates and invertebrates encodes visual signals with both spikes and graded signals. [•] In vertebrates, ‘digitization’ of the visual signal begins in the axonal system of bipolar cells. [•] Spikes and graded signals are both transmitted through ribbon synapses. [Copyright &y& Elsevier]

Future communication system requires large bandwidths to achieve high data rates, thus rendering analog-to-digital conversion (ADC) a bottleneck due to its high power consumption. In this paper, we consider monobit receivers for QPSK. The optimal monobit receiver under Nyquist sampling is obtained and its performance is analyzed. Then, a suboptimal but low-complexity receiver is proposed. The effect of imbalances between In-phase (I) and Quadrature (Q) branches is carefully examined. To combat the performance loss due to IQ imbalances, monobit receivers based on double training sequences and eight-sector phase quantization are proposed. Numerical simulations show that the low-complexity suboptimal receiver suffers 3dB signal-to-noise-ratio (SNR) loss in additive white Gaussian noise (AWGN) channels and only 1dB SNR loss in multipath channels compared with matched-filter monobit receiver with perfect channel state information (CSI). It is further demonstrated that the amplitude imbalance has essentially no effect on monobit receivers. In AWGN channels, receivers based on double training sequences can efficiently compensate for the SNR loss without complexity increase, while receivers with eight-sector phase quantization can almost completely eliminate the SNR loss caused by IQ imbalances. In dense multipath channels, the effect of imbalances on monobit receivers is slight. [ABSTRACT FROM AUTHOR]

Conventional continuous-time \Delta \Sigma modulators that use non-return-to-zero (NRZ) feedback DACs suffer from distortion due to intersymbol interference (ISI) and are sensitive to clock jitter. Using a return-to-zero (RZ) DAC solves the problem of ISI, but exacerbates clock jitter sensitivity. The clock jitter sensitivity of an NRZ DAC can be reduced using a switched-capacitor (SC) DAC, but the large peak-to-average ratio of the DAC waveform degrades modulator linearity. In this work, we introduce the switched-capacitor return-to-zero (SCRZ) DAC, which combines the low clock jitter sensitivity of the SC DAC with the low distortion of an RZ DAC. The efficacy of the SCRZ principle is borne out by measurement results from a modulator that achieves a DR/SNR/SNDR of 87.1/84.5/82.3 dB in a 2 MHz bandwidth while dissipating 16.5 mW from a 1.8-V supply. The converter, designed in a 0.18-\mu \m CMOS technology, reduces clock jitter sensitivity by 28 dB when compared with a traditional RZ DAC. [ABSTRACT FROM AUTHOR]

This paper describes an incremental converter based on a second order ΣΔ modulator. The scheme uses a 3-bit DAC with inherent linearity, an optimal reset of integrators, and gives rise to an effective offset cancellation with a novel technique based on single or double chopping. The circuit, fabricated in a mixed 0.18-0.6 μm CMOS technology, obtains 1.5-μV residual offset with 2V fully differential range. The measured resolution is 19 bit obtained with 512 clock periods. [ABSTRACT FROM AUTHOR]

A 7-bit, 2.2-GS/s time-interleaved subranging CMOS analog-to-digital converter (ADC) for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate gain mismatches within channels. Moreover, the channel offset mismatches are calibrated through the digital- controlled corrective current sources embedded in the track-and-hold amplifiers of each sub-ADC. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm^2 chip area and consuming 40 mW at 2.2 GS/s from a 1 V supply. Measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate. The effective number of bits (ENOB) is 6.0 bits at Nyquist rate, and the figure-of-merit (F.O.M.) is 0.28 pJ/conv.-step. This prototype has also been integrated into a gigabit self-healing wireless transceiver SoC. [ABSTRACT FROM AUTHOR]

The recently introduced compressive sensing (CS) framework enables digital signal acquisition systems to take advantage of signal structures beyond bandlimitedness. Indeed, the number of CS measurements required for stable reconstruction is closer to the order of the signal complexity than the Nyquist rate. To date, the CS theory has focused on real-valued measurements, but in practice measurements are mapped to bits from a finite alphabet. Moreover, in many potential applications the total number of measurement bits is constrained, which suggests a tradeoff between the number of measurements and the number of bits per measurement. We study this situation in this paper and show that there exist two distinct regimes of operation that correspond to high/low signal-to-noise ratio (SNR). In the measurement compression (MC) regime, a high SNR favors acquiring fewer measurements with more bits per measurement; in the quantization compression (QC) regime, a low SNR favors acquiring more measurements with fewer bits per measurement. A surprise from our analysis and experiments is that in many practical applications it is better to operate in the QC regime, even acquiring as few as 1 bit per measurement. [ABSTRACT FROM PUBLISHER]

In this paper, we propose low precision BER-optimal analog-to-digital converters (ADC) where quantization levels and thresholds are set nonuniformly to minimize the bit-error rate (BER) in a high data rate communication link. This is in contrast to how ADCs are used today, in which they act as transparent waveform preservers. Simulations for various communication channels show that for 2-PAM modulation, the BER-optimal ADC achieves shaping gains that range from 2.5 dB for channels with low intersymbol interference (ISI) to more than 30 dB for channels with high levels of ISI. Moreover, a 3-bit BER-optimal ADC achieves the same or even lower BER than a 4-bit uniform ADC. With a DFE and a high-ISI channel, a 3-bit BER-optimal ADC achieves lower BER than a 5-bit uniform ADC. [ABSTRACT FROM PUBLISHER]

This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-\mum CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power. [ABSTRACT FROM PUBLISHER]

This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400 aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90 nm CMOS occupies only 0.11 mm^2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5 GS/s at 0.75 V supply, and 1 GS/s at 1 V supply with 0.47 mW and 1.6 mW power consumption respectively. With an ENOB of 4.7 and 4.8 bits, this leads to energy efficiencies of 36 and 57 fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes. [ABSTRACT FROM PUBLISHER]