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The evolution of Digital Predistortion (DPD) for Power Amplifier (PA) linearization in wireless communications has seen a natural progression towards increasingly complex DPD models. This complexity directly correlates with improved accuracy in modeling PAs, thereby enhancing the linearization performance of DPD systems. As the demand for bandwidth and PA operation frequencies continues to rise, there is a growing trend towards achieving higher accuracy at the expense of increased complexity. This trend poses challenges for DPD design, necessitating the introduction of more complex algorithms to ensure effective PA linearization. This phenomenon is especially apparent in Volterra Series DPD algorithms, which are widely used for modelling nonlinear systems like PAs. This paper showcases the steps of reducing the modelling operations complexity of the Simplified Volterra (SV) method. The treated SV method presented in this paper is compared against the original SV method through simulation. The DPD model operations complexity is evaluated using the number of required multiplication operations. The DPD PA linearization performance is evaluated with respective model’s Normalized Mean Square Error (NMSE). A 57% reduction on the number of multiplication operations is observed in the treated SV against the original SV. Measured NMSE is similar for both models, indicating the treated SV model achieves this reduction in complexity without sacrificing linearization performance. [ABSTRACT FROM AUTHOR]

Radio frequency (RF) power amplifiers (PA) are efficiently linearized by adaptive digital predistortion (DPD). However, performance of DPD is severely degraded in presence of transmitter’s frequency-selective in-phase/quadrature (I/Q) imbalance. We propose DPD/IQ method that compensates the effects of transmitter I/Q imbalance and PA nonlinearity, which is dedicated for implementation in low-cost software radio defined (SDR) cellular base stations. The advantage of DPD/IQ is low complexity in terms of reduced number of DPD coefficients which provides significant savings of FPGA resources. The DPD/IQ has been evaluated after method has been implemented in SDR board. Measured results clearly demonstrate efficient compensation of PA and transceiver impairments enabling transmission of wide bandwidth waveforms and realization of sophisticated modulation schemes. Improvement in image rejection ratio of 10-15dB is achieved. Considering compensation of PA nonlinearities, the ACPR at PA output is decreased by 15dBc.

This paper proposes a novel predistorter architecture suitable for hybrid baseband/RF implementation. The distortion function is split into a memory polynomial and an AM/AM only look-up table (LUT). The memory polynomial function is to be applied in the baseband digital domain whereas the LUT predistorter is suitable for low complexity implementation in either the baseband digital or the RF analog domains. The proposed model was compared to benchmark models using 20MHz and 40MHz wide 5G test signals, and found to be superior in terms of adjacent channel leakage ratio performance and complexity. Experimental results showed that the model can achieve ACLR levels of better than −50dBC with a relatively low number of coefficients. The proposed model requires around 20% less coefficients than the reverse twin-nonlinear two-box model, and achieves slightly better ACLR while easing the analog implementation of the static nonlinearity predistortion function. Most importantly, the low-complexity hybrid implementation of the proposed model can drastically reduce the speed requirements in the digital to analog converter of the signal transmit path by up to 80% when compared to traditional DPD systems.

In this paper, an efficient neural-network-based adaptive DPD design which performs well under power varying conditions is presented. The DPD design is derived on the basis of the envelop time-delay neural network (ETDNN). The redefined ETDNN-DPD requires the part of parameter updates, which enables to adapt it to the rapid change of power amplifier (PA) distortion. Additionally, the redefined ETDNN-DPD also maintains the stability of the compensation performances under varying power condition while its structure is pruned by the structured pruning. Furthermore, to verify its practical use, we also propose the weight scaling technique, which reduces multiplications of the redefined ETDNN-DPD, and applied it to the implementation of the redefined ETDNN-DPD on FPGA. Compared FPGA-implemented ETDNN-DPD with FPGA-implemented conventional memory polynomial DPD, we verified that our proposed DPD achieved 3.2 dB better error vector magnitude (EVM) while lower hardware resource utilization at the fixed power level. Moreover, our proposed DPD kept better performance under the varying power condition only by the partial update of its parameters than memory polynomial DPD.

Radio frequency (RF) power amplifiers (PA) are efficiently linearized by adaptive digital predistortion (DPD). However, performance of DPD is severely degraded in presence of transmitter's frequency-selective in-phase/'quadrature (I/Q) imbalance. We propose the DPD/IQ method that compensates the effects of transmitter 's I/Q imbalance and PA nonlinearity and is dedicated for implementation in low-cost software defined radio (SDR) cellular base stations. The advantage of DPD/IQ is low complexity in terms of reduced number of DPD coefficients which provides significant savings of FPGA resources. The performance of DPD/IQ has been evaluated after the method has been implemented in SDR board. Measured results clearly demonstrate efficient compensation of PA and transceiver impairments enabling transmission of wide bandwidth waveforms and realization of sophisticated modulation schemes. Improvement in image rejection ratio of 10-15 dB is achieved. Considering compensation of PA nonlinearities, the ACPR at PA output is decreased by 15 dBc. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient neural-network-based digital predistortion (DPD), named as envelope time-delay neural network (ETDNN) DPD. The method complies with the physical characteristics of radio-frequency (RF) power amplifiers (PAs) and uses a more compact DPD model than the conventional neural-network-based DPD. Additionally, a structured pruning technique is presented and used to reduce the computational complexity. It is shown that the resulting ETDNN obtained after applying pruning becomes so sparse that its complexity is comparable to that of conventional DPDs such as memory polynomial(MP) and generalized memory polynomial (GMP), while the degradation in performance due to the pruning is negligible. In an experiment on a 3.5-GHz GaN Doherty power amplifier (PA), our method with the proposed pruning had only one-thirtieth the computational complexity of the conventional neural-network-based DPD for the same adjacent channel leakage ratio (ACLR). Moreover, compared with memory-polynomial-based digital predistortion, our method with the proposed pruning achieved a 7-dB improvement in ACLR, despite it having lower computational complexity.

In this paper, a software-defined radio (SDR) based transceiver system is designed and implemented on the system-on-chip (SoC) platform, which consists of a high-speed Arm embedded processor and a reconfigurable field-programmable gate array (FPGA). In the proposed SDR transceiver, the real-time baseband signal generation and adaptive digital predistortion (ADPD) units are implemented on the SoC platform. Memory polynomial model based ADPD solution is implemented to linearize the radio frequency (RF) power amplifiers (PAs). The implementation of the ADPD on a reconfigurable FPGA platform makes the system flexible and cost-effective. The PA characterization, in terms of model extraction and coefficient calculation, is done in real-time. These calculated coefficients are updated in the transmission path to precondition the transmitted signal before it is applied to the PA. The proposed ADPD is applied at the baseband level. Therefore, it can be used for different classes of PA operating at different RF carrier frequencies. A long-term evolution (LTE) signal with 20 MHz bandwidth and 11 dB peak to average power ratio (PAPR) is used for simulation and measurement purposes. The LTE signal is amplified using a GaN-based harmonically tuned continuous Class-F PA in measurement. The performance of the implemented ADPD scheme is analyzed in terms of NMSE, ACPR and EVM.

This paper introduces the measurement/modeling of a nonlinear RF power amplifier (PA) model extraction of spectral overlaps and peak-to-average power ratio (PAPR). The modeling consists of a weighted cubic-spline basis approach that preserves a relationship by its generic asymptotic properties under adequate PAPR regime to estimate signaling conditions. To jointly provide a data-driven model a field-programmable gate array (FPGA) testbed is proposed, in which a precomputed approach with deterministic signals is used to perform: (i) parameter estimation; (ii) adequate PAPR levels; (iii) reinforcement of sparsity data with extrapolation fitting; and (iv) FPGA implementation. Moreover, a technique for parameter identification is introduced to provide insights of a digital predistortion (DPD) PA model extraction with cubic-spline to efficiently improve the linearization performance. A theoretical analysis that states on the benefits from coefficients precomputation to preserve multiple-input multiple-output (MIMO) relationship with antenna selection technique estimation, is also proposed. Also, a Cholesky FPGA algorithm implementation to matrix inversion is validated, which aims to show the good numerical and computational complexity for up to $64\times 64$ MIMO arrays. Experimental results prove a good accuracy and close agreement between the modeling and estimation yielding a reliable model with a little overfitting.

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), ...) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within "reasonably above" PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR − 50 dBc, at 10 W LTE modulated PA output, antenna point and PA output power of 39.5 dBm. [ABSTRACT FROM AUTHOR]

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In this paper, a low-complexity model is proposed for linearizing power amplifiers with memory effects using the digital predistortion (DPD) technique. In the proposed model, the linear, low-order nonlinear and highorder nonlinear memory effects are computed separately to provide flexibility in controlling the model parameters so that both high performance and low model complexity can be achieved. The performance of the proposed model is assessed based on experimental measurements of a commercial class AB power amplifier by applying a single-carrier wideband code division multiple access (WCDMA) signal. The linearity performance and the model complexity of the proposed model are compared with the memory polynomial (MP) model and the DPD with single-feedback model. The experimental results show that the proposed model outperforms the latter model by 5 dB in terms of adjacent channel leakage power ratio (ACLR) with comparable complexity. Compared to MP model, the proposed model shows improved ACLR performance by 10.8 dB with a reduction in the complexity by 17% in terms of number of floating-point operations (FLOPs) and 18% in terms of number of model coefficients. [ABSTRACT FROM AUTHOR]

In this paper, a novel weighted memory polynomial (WMP)-based model is proposed for wireless transmitters and radio-frequency power amplifiers' (PAs) behavioral modeling and predistortion. The new model introduces an instantaneous-power-dependent weight function on the static and dynamic terms of the conventional memory polynomial (MP) model. Experimental validation in both modeling and predistortion contexts was performed on a PA prototype driven by a 20-MHz Long Term Evolution signal. The proposed model was assessed against the standard MP model. The experimental results demonstrate the superiority of the proposed polynomial in behavioral modeling applications as it results in up to 50% (3-dB) improvement in the normalized mean square error for the same number of coefficients. The model robustness was then validated by using a second test signal applied to two Doherty PAs using different transistor technologies. Furthermore, when applied for digital predistortion, the proposed WMP function achieves the same performance as the state-of-art MP while requiring approximately 50% less coefficients. [ABSTRACT FROM PUBLISHER]

Power amplifiers are widely used in RF broadcasting applications. However, they tend to exhibit nonlinear behavior that distorts the input signals both in the time and frequency domains, consequently motivating the development of techniques, such as digital predistortion, which can counteract this behavior. Among the challenges facing the identification of an amplifier's digital predistorter and behavioral model is finding the correct model dimensions, as this requires a priori knowledge of multiple parameters. In this paper, a predistorter based on a cluster-based implementation particle swarm optimization technique with embedded model-size estimation capability is presented. The validation of the proposed technique on a Doherty power amplifier prototype demonstrates its ability to efficiently find the dimensions of a memory polynomial based digital predistorter, while accurately estimating its coefficients. [ABSTRACT FROM PUBLISHER]

In this letter, a compact envelope-memory polynomial based model, suitable for forward and reverse modeling of weakly nonlinear wireless transmitters and power amplifiers (PAs) exhibiting electrical memory effects, is presented. This model is implemented in a complex gain based architecture and takes advantage of the dependency of PA nonlinearity on the magnitude of the input signal. Contrary to conventional memory polynomials, the proposed model can be implemented in baseband, as well as in radio frequency, digital predistorters. A 100-W average power transmitter is used for experimental validation of the forward and reverse models. Both forward and reverse modeling results obtained with the proposed model are comparable to that of the conventional memory polynomial. [ABSTRACT FROM PUBLISHER]

Amplification of signals with fluctuating envelopes inevitably leads to distortion because of nonlinear behavior of the power amplifier (PA). Digital predistortion can counteract these nonlinear effects. In this letter, the crosscorrelation predistorter is described and the effects of quantization in the feedback path are presented. One of the effects is that the quantization noise is correlated with the signal to be quantized, resulting in reduced performance of predistortion. A technique to reduce these effects is to inject a dither signal before quantization. Because of the quantization noise and dither signal, more data has to be used to obtain estimates of the PA behavior that are accurate enough for effective predistortion. [ABSTRACT FROM PUBLISHER]