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The electrical and dielectric properties of Ba0.8Sr0.2TiO3 thin films and Ba0.8Sr0.2TiO3/ZrO2 multilayer thin films deposited on Pt/Ti/SiO2/Si substrates by sol-gel method are studied. The temperature dependence of the dielectric properties for pure Ba0.8Sr0.2TiO3 film and Ba0.8Sr0.2TiO3/ZrO2 multilayer films has been studied in the temperature range from 90 to 500 K. Both dielectric constant and dielectric loss exhibit minimal dispersion as a function of temperature in this range. It is observed that dielectric constant, dielectric loss, and tunability are reduced for multilayer thin films. Additionally, the ferroelectricity disappears in multilayer thin films. Our results show that the multilayered Ba0.8Sr0.2TiO3/ZrO2 design has excellent dielectric properties and they are stable over a broad temperature range (90-500 K), thereby making them excellent candidates for the next generation of enhanced performance temperature stable microwave devices. [ABSTRACT FROM AUTHOR]

This paper investigates the p-Ge/Al2O3/ZrO2/TiN gate stacks that were subjected to different slot plane antenna oxidation (SPAO) conditions: 1) prior to any high-k atomic layer deposition (ALD); 2) in between Al2O3 and ZrO2ALD layers; and 3) after the ALD of high- k layers. The carrier transport mechanisms as a function of temperature on these samples were observed to be different. The SPAO treatment effectively removes the trap centers in ZrO2 and Al2O3 layers depending on the SPAO treatments. Fowler-Nordheim tunneling seems to be the dominant transport mechanism at high field range when SPAO was performed after the high- k layers were deposited. On the other hand, Poole-Frenkel emission and hopping conduction mechanism are dominant for other two samples in both gate electron injection and substrate electron injection (SEI) modes. The trap center ( \phi \text{t1} = {0.13} eV) remains in the ZrO2 when ZrO2 is not subjected to the SPAO. Trap energy level \phi \text{t1} (0.13 eV) was removed and \phi \text{t2} (0.27 eV) still exists when only Al2O3 oxide layer was exposed to SPAO. Hopping distance, a (about 0.3 nm) is extracted by hopping conduction model. After time dependent dielectric breakdown measurement, it was found that if GeO2 exists at the interface then it can be degraded easily by SEI stress. On the other hand, if SPAO was processed in between the high- k layers the formation of a GeOx layer enhances the interface quality and provides better immunity to degradation under stress. [ABSTRACT FROM PUBLISHER]

This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlOx with extremely low Al (<3% Al/(Al+Hf)) incorporation in the Hf based high-k dielectrics. The defect activation energy estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V+/V2+, are the primary source of defects in these dielectrics. When Al is added in HfO2, the V+ type defects with a defect activation energy of Ea ~ 0.2 eV modify to V2+ type to Ea ~ 0.1 eV with reference to the Si conduction band. When devices were stressed in the gate injection mode for 1000 s, more V+ type defects are generated and Ea reverts back to ~0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO2 contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C. [ABSTRACT FROM AUTHOR]

This work examines the inherent asymmetry on breakdown characteristics of the interfacial layer (IL) and high-κ layer in the overall gate-stack breakdown. Ramped and constant voltage stresses were applied on atomic-layer-deposited TiN/HfO2/SiO2 gate stacks. Under ramped stress when a thin high-κ layer (≤3.3 nm) is used, IL is responsible for the overall gate-stack breakdown; otherwise, the breakdown is initiated by the high-κ layer. Under constant voltage stress the gate stack went through many degradation mechanisms, such as charge trapping and defect generation, soft breakdown, progressive breakdown, and finally hard breakdown. In addition, when the breakdown field of ILs grown under various process conditions was compared, it was observed that for a fixed IL thickness, breakdown field does not depend on predeposition surface treatment; rather, it is a function of the quality of IL. Stress-induced leakage current was also studied to correlate with the breakdown behavior. [ABSTRACT FROM AUTHOR]

We have observed charge trapping during constant voltage stress in Hf-based high-K dielectrics at deep traps as well as at the shallow traps. ΛVFB and leakage current dependence on these deep traps further suggest that trapping at deep levels inhibits fast ΛVT recovery. The earlier findings where charge trapping seemed to be very transient due to the presence of a large number of shallow traps and trapped charge could be eliminated by applying a reverse direction electric field may no longer be valid. The experimentally observed trap energy levels from low-temperature measurements establish a relationship between the origin of the deep traps and their dependence on O vacancy formation in Hf-silicate-based films. Substrate hot electron injection gives rise to significant electron trapping and slow post-stress recovery under negative bias conditions, which confirms that O-vacancy-induced deep defects determine the transient behavior in Hf-silicate-based high-K gate dielectrics. It is further shown that negative-U transition to deep defects is responsible for trap-assisted tunneling under substrate injection. A fraction of the injected electrons remains trapped at the deep defects and gives rise to significant ΛVFB. This has the potential to be the ultimate limiting factor for the long-term reliability of Hf-based high-κ gate dielectrics. [ABSTRACT FROM AUTHOR]

The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavior of n- and p-channel MOSFETs with high-κ gate dielectrics and metal gates is investigated. Decreasing the interfacial layer thickness from 0.8 to 0.4 nm affects the 1/f noise in two ways. 1) The mobility fluctuations mechanism becomes the main source of 1/f noise not only on pMOS devices, as usually observed, but also on nMOS devices. 2) A significant increase of the Hooge's parameter is observed for both types of MOSFETs. These experimental findings indicate that bringing the high-κ layer closer to the SiSiO2 interface enhances the 1/f noise mainly due to mobility fluctuations. [ABSTRACT FROM AUTHOR]

Abstract: The effects of interfacial layer quality on the low-frequency noise behavior of p-channel MOSFETs with high-κ gate dielectric and metal gate are investigated. Devices with chemically grown SiO2 interfacial layers (0.8nm) are compared with N2O (0.8nm) interfacial oxides. A 0.4nm SiO2 interfacial layer device is used for comparison purposes. A cross-over kind of behavior has been observed in N2O devices, which occur at lower gate voltages (∼1.2–1.3V) when normalized spectral densities and input referred noise are investigated. This behavior is found to be closely related to the observed transconductance variation in these devices. The dominant mechanism of 1/f noise is found to be Hooge’s mobility fluctuations. Hooge’s parameter, as a figure of merit, shows an increase for 0.4nm devices when compared to 0.8nm devices, while 0.8nm N2O devices confirm their cross-over nature. [Copyright &y& Elsevier]

Abstract: The low-frequency (LF) noise of n-MOSFETs with a 1.5nm SiON gate oxide is studied for different gate materials, namely, a polycrystalline (poly) silicon gate, a fully nickelsilicided (FUSI) gate and a NiSi FUSI gate deposited on 10 cycles of HfO2. The principal aim is to identify the most likely origin of the predominant 1/f noise in the thin gate oxide devices by investigating the impact of the gate electrode processing. It is reported that the lowest input-referred voltage noise spectral density (S VG) in linear operation for a gate voltage at the threshold voltage is found for the FUSI transistor, while adding 10 cycles of HfO2 enhances markedly the noise magnitude. The 1/f noise characteristic behaves according to the number fluctuations theory so that the results are interpreted in terms of trapping and de-trapping of channel carriers by defects in the gate dielectric layer. Therefore, the marked effect of the gate material is at present ascribed to the different trap density in the vicinity of the gate-SiON interface, which is derived from the LF noise spectra. [Copyright &y& Elsevier]

Abstract: The aim of this paper is to study the 1/f noise performance of n- and p-channel MOSFETs with different Hf-based gate stacks, deposited by MOCVD and using metal (PVD TaN) as a gate material. The drain current dependence is different for n- and p- channel devices over the noise spectra, showing different noise origin mechanisms – mobility fluctuations for pMOS and number fluctuations for nMOS. Asymmetric trap density distributions with energy between n- and pMOS have been observed which is a possible reason for the observed lower noise magnitude in pMOS devices. A fair comparison using Hooge’s parameter and trap densities as figures of merit shows weak correlation on the Hf-composition, allowing a large window for gate stack processing of devices. [Copyright &y& Elsevier]

The article presents information about the science and technology of dielectric materials. They have wide applications throughout the electronics, microwave, communication, and aerospace industries. Silicon dioxide has been the most significant and ubiquitous dielectric for several decades. This material is used as the gate dielectric in complementary metal oxide semiconductor technology, which dominates the modern electronics industry. A dielectric material is deposited as a thin film, on p- or n-type semiconductor surfaces by various techniques including thermal oxidation, sputtering, and chemical vapor deposition.