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Dielectric breakdown mechanism of gate dielectrics has been reconsidered with SiO2 films of various thicknesses ranging from 3.6 to 9.5 nm. Careful time-dependent dielectric breakdown (TDDB) measurements have realized the detection of anomalous lifetime (TBD) lowering than the expectation from generally accepted power-law (PL) model at relatively low-voltage region in 6- and 6.5-nm-thick films. Analysis from the viewpoint of the hole and electron fluence to breakdown (QBD,hole and QBD,el) has demonstrated the dominant carrier change(DCC) from hole to electron with the lowering of the stress voltage. These results strongly support the DCC model. The DCC model provides stress voltage-independent defect generation efficiencies of electron and of hole at the stress voltage region where each carrier dominates the breakdown, while the PL model provides the stress voltage-dependent efficiency. The DCC model is also capable to explain the empirically reported linear electric field (E) dependence of TBD in a wide range of stress voltage which supports the thermochemical model (E-model). Therefore, it is expected that the DCC model can also be employed in the lifetime prediction of gate dielectrics thicker than ~5 nm, where the E-model is generally employed in the lifetime insurance of actual market products. The DCC model is expected to give longer predicted TDDB lifetimes at the actual device operating conditions in most devices than the E-model and other models and, hence, more aggressive usage of gate dielectric films can be realized. [ABSTRACT FROM AUTHOR]

Anomalous Time Dependent Dielectric Breakdown (TDDB) statistics of thick gate dielectrics, i.e., too large stress field/voltage dependence and nonlinear Weibull plot of TDDB lifetime, have been observed. Through the analysis of behaviors under the TDDB stress and also the comparison with thin gate dielectrics, it has been revealed that just the intrinsic charging of injected carriers to initial and stress-generated defects induces the dynamic stress relaxation under the constant–voltage stress, resulting in anomalous TDDB statistics. This charging-induced dynamic stress relaxation (CiDSR) effect reduces the validity of well-known Weibull statistics and prevents us from accurately predicting TDDB lifetimes utilizing various conventional scaling procedures, such as area, failure rate, and temperature scaling. Impact of the CiDSR effect increases with the thickness of gate dielectrics and the development of an appropriate lifetime prediction method is urgent not only for Si devices but also for various compound devices having thick gate dielectrics, such as GaN and SiC power devices. [ABSTRACT FROM PUBLISHER]