Search

A monolithic pixel sensor with high spatial granularity (35 × 40 μm2) is presented, aiming at thermal neutron detection and imaging. The device is made using the CMOS SOIPIX technology, with Deep Reactive-Ion Etching post-processing on the backside to obtain high aspect-ratio cavities that will be filled with neutron converters. This is the first monolithic 3D sensor ever reported. Owing to the microstructured backside, a neutron detection efficiency up to 30% can be achieved with a 10B converter, as estimated by the Geant4 simulations. Each pixel includes circuitry that allows a large dynamic range and energy discrimination and charge-sharing information between neighboring pixels, with a power dissipation of 10 µW per pixel at 1.8 V power supply. The initial results from the experimental characterization of a first test-chip prototype (array of 25 × 25 pixels) in the laboratory are also reported, dealing with functional tests using alpha particles with energy compatible with the reaction products of neutrons with the converter materials, which validate the device design. [ABSTRACT FROM AUTHOR]

A digital asynchronous logic is proposed as a generic matrix readout for Monolithic active pixel sensors. The architecture is implemented for pixel pitch ranging from 18 to 30 µm. Post-layout simulations with realistic hit shapes and rates up to 200 MHz/cm 2 show that time stamping at the 20 ns level can be achieved for a digital power cost below 10 mW/cm 2. [ABSTRACT FROM AUTHOR]

This work is focused on the design and the experimental characterization of an analog channel developed for the readout of lithium-drifted silicon detectors of the General AntiParticle Spectrometer (GAPS) experiment aimed at the search for dark matter. The instrument is designed for the identification of antideuteron particles from cosmic rays during an Antarctic balloon mission scheduled for late 2022. A low-noise analog front-end, featuring a dynamic signal compression to comply with the wide input range, has been designed in commercial 180-nm CMOS technology. The channel was fabricated in 2018 and is the first building block toward the development of a multichannel readout ASIC. The article will provide a description of the design criteria, the architecture of the channel, and a summary of the results of the experimental characterization. [ABSTRACT FROM AUTHOR]

A new pixel detector for the CMS experiment is being built, owing to the instantaneous luminosities anticipated for the Phase I Upgrade of the LHC. The new CMS pixel detector provides four-hit tracking while featuring a significantly reduced material budget as well as new cooling and powering schemes. A new front-end readout chip mitigates buffering and bandwidth limitations, and comprises a low-threshold comparator. These improvements allow the new pixel detector to sustain and improve the efficiency of the current pixel tracker at the increased requirements imposed by high luminosities and pile-up. This contribution gives an overview of the design of the upgraded pixel detector and the status of the upgrade project, and presents test beam performance measurements of the production read-out chip. [ABSTRACT FROM AUTHOR]

The paper presents first results from the Front-End Board (FEB) with the biggest Cyclone® V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled up to 250 MSps @ 14-bit resolution. Considered sampling for the planned upgrade of the Pierre Auger surface detector array is 120 MSps, however, the FEB has been developed with external anti-aliasing filters to keep a maximal flexibility. Six channels are targeted to the SD, two the rest for other experiments like: Auger Engineering Radio Array and additional muon counters. More channels and higher sampling generate larger size of registered events. We used the standard radio channel for a radio transmission from the detectors to the Central Data Acquisition Station (CDAS) to avoid at present a significant modification of a software in both sides: the detector and the CDAS (planned in a future for a final design). Several variants of the FPGA code were tested for 120, 160, 200 and even 240 MSps DAQ. Tests confirmed a stability and reliability of the FEB design in real pampas conditions with more than 40°C daily temperature variation and a strong sun exposition with a limited power budget only from a single solar panel. Seven FEBs have been deployed in a hexagon of test detectors on a dedicated Engineering Array. [ABSTRACT FROM PUBLISHER]

This work is concerned with the design of a low-noise Charge Sensitive Amplifier featuring a dynamic signal compression based on the non-linear features of an inversion-mode MOS capacitor. These features make the device suitable for applications where a non-linear characteristic of the front-end is required, such as in imaging instrumentation for free electron laser experiments. The aim of the paper is to discuss a methodology for the proper design of the feedback network enabling the dynamic signal compression. Starting from this compression solution, the design of a low-noise Charge Sensitive Amplifier is also discussed. The study has been carried out by referring to a 65 nm CMOS technology. [ABSTRACT FROM AUTHOR]

In this paper, we report on the recent development of a 32-channel low-noise front-end readout ASIC for cadmium zinc telluride (CdZnTe) X-ray and \gamma -ray detectors. Each readout channel includes a charge sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer. The readout ASIC is implemented using TSMC 0.35 - \mu \m mixed-signal CMOS technology, the die size of the prototype chip is 2.2~\mm \times 4.8~\mm. At room temperature, the equivalent noise level of a typical channel reaches 133~\e^ - (rms) with the input parasitic capacitance of 0 pF for the average power consumption of 2.8 mW per channel. The linearity error is less than \pm 2\% and the input energy dynamic range of the readout ASIC is from 10 keV to 1 MeV. The crosstalk between the channels is less than 0.4%. By connecting the readout ASIC to a CdZnTe detector, we obtained a \gamma -ray spectrum, the energy resolution is 1.8% at the 662-keV line of ^137Cs source. [ABSTRACT FROM AUTHOR]

The surface detector (SD) array of the Pierre Auger Observatory needs an upgrade which allows space for more complex triggers with higher bandwidth and greater dynamic range. To this end this paper presents a front-end board (FEB) with the largest Cyclone V E FPGA 5CEFA9F31I7N. It supports eight channels sampled with max. 250 MSps@14-bit resolution. Considered sampling for the SD is 120 MSps; however, the FEB has been developed with external anti-aliasing filters to retain maximal flexibility. Six channels are targeted at the SD, two are reserved for other experiments like: Auger Engineering Radio Array and additional muon counters. The FEB is an intermediate design plugged into a unified board communicating with a micro-controller at 40 MHz; however, it provides 250 MSPs sampling with an 18-bit dynamic range, is equipped with a virtual NIOS processor and supports 256 MB of SDRAM as well as an implemented spectral trigger based on the discrete cosine transform for detection of very inclined “old” showers. The FEB can also support neural network development for detection of “young” showers, potentially generated by neutrinos. A single FEB was already tested in the Auger surface detector in Malargüe (Argentina) for 120 and 160 MSps. Preliminary tests showed perfect stability of data acquisition for sampling frequency three or four times greater. They allowed optimization of the design before deployment of seven or eight FEBs for several months of continuous tests in the engineering array. [ABSTRACT FROM PUBLISHER]

This work describes new electronics for the EXOGAM2 (HP-Ge detector array) and NEDA (BC501A-based neutron detector array). A new digitizing card with high resolution has been designed for gamma-ray and neutron spectroscopy experiments. The higher bandwidth requirement of the NEDA signals, together with the necessity for accuracy, require a high sampling rate in order to preserve the shape for real-time Pulse Shape Analysis (PSA). [ABSTRACT FROM AUTHOR]

This paper presents the architecture, design and test results of an ASIC specifically designed for the readout of gaseous detectors. The primary application is the readout of the Linear Collider Time Projection Chamber. The small area available (4~\ mm^2 /\ channel) requires an innovative design, where sensitive analog components and massive digital functionalities are integrated on the same chip. Moreover, shut down (power pulsing) features are necessary in order to reduce the power consumption. The Super-Altro is a 16-channel demonstrator ASIC involving analog and digital signal processing. Each channel contains a low noise Pre-Amplifier and Shaping Amplifier (PASA), a pipeline ADC, and a Digital Signal Processor (DSP). The PASA is programmable in terms of gain and shaping time and can operate with both positive and negative polarities of input charge. The 10-bit ADC samples the output of the PASA at a frequency up to 40 MHz before providing the digitized signal to the DSP which performs baseline subtraction, signal conditioning, drift correction and zero suppression. The chip has been fabricated in a 130 nm CMOS technology. Test measurements show correct functionality of the full system, and demonstrate that, using appropriate design techniques, the extensive digital circuitries produce little or no degradation of analog performance (particularly noise). [ABSTRACT FROM PUBLISHER]

Final results on a CMOS 0.18 µm front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 µm is briefly presented. [ABSTRACT FROM AUTHOR]

Abstract: In order to confirm benefits of a deep sub-micron FD-SOI and to identify possible issues concerning front-end circuits with the FD-SOI, we have submitted a small design to Oki Electric Industry Co., Ltd. via the multi-chip project service of VDEC, the University of Tokyo. The initial test results and future plans for development are presented. [Copyright &y& Elsevier]

Abstract: Silicon Photomultipliers, though still under development for mass production, may be an alternative to traditional Vacuum Photomultipliers Tubes (VPMT). As a consequence, electronic front-ends initially designed for VPMT will need to be modified. In this simulation, an improved architecture is presented which is able to obtain impact position and depth of interaction of a gamma ray within a continuous scintillation crystal, using either kind of PM. A current sensitive preamplifier stage with individual gain adjustment interfaces the multi-anode PM outputs with a current division resistor network. The preamplifier stage allows to improve front-end processing delay and temporal resolution behavior as well as to increase impact position calculation resolution. Depth of interaction (DOI) is calculated from the width of the scintillation light distribution, which is related to the sum of voltages in resistor network input nodes. This operation is done by means of a high-speed current mode scheme. [Copyright &y& Elsevier]

Abstract: The goal of this work is to provide an extensive analysis of the noise performances which can be attained by detector front-end integrated circuits in the 0.13μm CMOS node. To estimate the noise limits of a front-end system in this CMOS generation, the paper presents the results of measurements carried out on NMOS and PMOS devices fabricated in a commercial process. Parameters extracted from experimental data are used to define design criteria for noise optimization in the perspective of future experimental environments (SLHC, ILC, Super B-Factory). [Copyright &y& Elsevier]

The data acquisition architecture for the tracking detector of the MECO experiment will consist of a preamplifier/discriminator feeding a buffered digitizer which will be controlled by programmable logic. The digitizer converts the timing and analog waveform into digital storage for later readout. In order to evaluate this conceptual design, a prototype system was assembled using an existing digitizer chip, which had similar characteristics to the one proposed for MECO. In this prototype system, the event readout sequence and trigger was controlled by a Xilinx FPGA, and gated data events were transferred for further processing to higher levels in the data stream. The system contained 64 input channels divided into four groups of 16 channels, and either anode or cathode signals could be processed. It could be operated in either an internal or external trigger mode. Test results are reported in this paper, including the maximum event rate, the system dead time, and the relationship between the system efficiency and the hitmap selection. Based on these test results, some improvements in the digitizer chip are discussed, and the specifications of our proposed digitizer are presented. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, a high-precision wide-range electronic front-end for resistive gas sensors is described. A flexible continuous time trans-resistance stage is followed by a switched capacitor incremental ADC. A smart DSP allows to reconfigure the front-end in order to achieve a resolution of 0.1% for a resistance ranging in [100Ω–10MΩ]. [Copyright &y& Elsevier]

Abstract: The read-out for Silicon Drift Detectors in the form of a VLSI chip is presented, 1 [1] Work supported by Catania University, MIUR and INFN. with a view to applications in High Energy Physics and space experiments. It is characterised by extremely low power dissipation, small noise and size. [Copyright &y& Elsevier]

Seed imbibition, absorption of water by a dry seed, is an essential process in which embryo hydration and root establishment occur. In natural environments, this process occurs beneath the soil, making it difficult to observe preliminary growth of seeds. This paper presents a new technique for tracking the imbibition of corn seeds. The proposed system is designed to measure imbibition through seed expansion and wirelessly transmit data, permitting the system to remain beneath the soil with the subject seed. The system consists of low-cost commercial off-the-shelf components and 3D-printed probes. The proposed system is optimized to measure the size of multiple seeds with a single Analog-to-Digital Converter (ADC) pin by utilizing the General-Purpose Input Output (GPIO) pins of the microcontroller, to reconfigure connections to supply voltage or ground. The circuit design of the system shows low power consumption compared to other conventional circuits and utilizes fewer components by taking advantage of the microcontroller GPIOs. Additionally, the proposed circuit design shows less error and insensitivity to the supply voltage variations. [ABSTRACT FROM AUTHOR]

The paper describes the requirements for the readout electronics and DAQ for the instrumentation of the forward region of the future detector at the international linear collider. The preliminary design is discussed. [ABSTRACT FROM AUTHOR]

This paper presents the design and experimental characterization of a 28 nm Complementary Metal Oxide Semiconductor (CMOS) Analog Front-End (AFE) for fast-tracking small-diameter Muon Drift-Tube (sMDT) detectors. The device exploits an innovative analog signal processing that allows a strong increase in the detection rate of events and significantly reduces the impact of fake/pile-up events, which often corrupt incident radiation energy events. The proposed device converts the input charge coming from incident radiations into voltage by a dedicated Charge-Sensitive Preamplifier (CSPreamp). Therefore, the fast-tracking concept relies on sampling the slope of the CSPreamp output voltage and using it for detecting both the incident event arrival instant and the amount of charge that has been effectively read out by MDT detectors. This avoids the long processing times intrinsically needed for baseline recovery transient, during which the detected signal can be severely corrupted by additional and unwanted extra-events, resulting in extra-charge (and thus in CSP output voltage extra-transient) during the signal roll-off. The proposed analog channel operates with a 5–100 fC input charge range and has a maximum dead-time of 200 ns (against the 545 ns of the state-of-the-art). It occupies 0.03 mm2 and consumes 1.9 mW from 1 V of supply voltage. [ABSTRACT FROM AUTHOR]

In the ALICE HMPID detector, Cherenkov photons are localised by measuring the charge induction on a MWPC cathode segmented into pads. Two ASICs have been developed: the Gassiplex07-3, which is an analogue 16-channels multiplexed front-end circuit dedicated to the readout of gaseous detector and the Dilogic-3, a sparse data scan digital processor. The combination of multiplexed and parallel-pipelined architecture allows to store several events between two L2 trigger and to transfer the 32-bits data words at a rate of 80 Mbytes per second through an optical data link. [Copyright &y& Elsevier]

Abstract: The FD-SOI technology is a fascinating LSI fabrication process as a possible radiation-tolerant device. In order to confirm benefits of the FD-SOI and expand application ranges in front-end electronics, we experimentally designed an analog front-end ASIC for X-ray CCD readout with the FD-SOI process. The circuit design was submitted to OKI Semiconductor Co., Ltd. via the multi-chip project as a part of the SOI pixel-detector R&D program in KEK. The ASIC contains seven readout channels using the correlated double sampling technique, and includes key circuit elements for a low-noise LSI. This paper describes the circuit design and the performance of the ASIC together with the radiation tolerance. [Copyright &y& Elsevier]