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Reed-Solomon (RS) codes are used in many storage systems for failure recovery. In popular software implementations, RS codes are defined by using a parity check matrix that is either a Cauchy matrix padded with an identity or a Vandermonde matrix. The encoding complexity can be reduced by searching for a Cauchy matrix that has a smaller number of 1s in its bit matrices or exploiting Reed-Muller (RM) transform in the Vandermonde matrix multiplication. This paper proposes two new approaches. In our first approach, different constructions of finite fields are explored to further reduce the number of ‘1’s in the bit matrices of the Cauchy matrix and a new searching method is developed to find the minimum number of ‘1’s. Our second approach defines RS codes using parity check matrices in the format of a Vandermonde matrix concatenated with an identity matrix so that the RS en/decoding can be simplified. A modified scheme is developed to enable the application of the RM transform such that the number of multiplications can be reduced.

We consider in this letter the problem of blind frame synchronization of Low Density Parity-Check (LDPC) codes. We present and compare new methods of blind frame synchronization based on the calculation of Likelihood functions of the syndrome. Simulation results show that the four proposed synchronization techniques are effective once applied to LDPC codes. The method that involves the maximization of the Likelihood Difference (LD) function of the parity-checks, presents the best results in terms of probability of false synchronization.

An efficient compact encoding process with the pipelining design of Low Density Parity Check (LDPC) Encoder with a two stage, three stage and Maximal Rate Pipelining (MRP) structures are proposed in this work. Comparatively, LDPC encoding is more complex than decoding. The complexity mainly referred to the mathematical computation involved in the design of LDPC encoder. There are several methods used to design reduced parity check matrix, one of the methods involved is the Gauss Elimination method. Conventional and wave pipelining techniques are implemented to overcome the disadvantages of the area, latency, etc., The designed architectures are synthesized in SYNOPSYS tool and implemented in the XC3S-250E FPGA device. The overheads like power and area are efficiently reduced by wave pipelining and their efficiency can be proved by synthesis report. This showcases that the LDPC Encoders require less memory by using MRP structure.

Syndrome-Trellis Code (STC) is a near-optimal convolutional method for adaptive steganography. Hitherto, the existing adaptive steganography commonly depends on the carefully designed distortion cost function, which controls the embedding position of the message in the cover signal. From another point of view, we implement adaptive steganography by improving the STC coding process (named Adaptive-STC). The parity-check matrix is the key to the encoding and extraction process of STC. In this work, we prove that the average embedding change probability of corresponding elements can be changed by adjusting its submatrix. Following that, we specially design an adaptive parity-check matrix to replace the designed distortion cost to restrict the embedding position. The generation of the adaptive parity-check matrix can be formulated as a multi-constrained integer programming problem in which the width of the submatrix is allocated at a fixed height. To solve this particular problem, we propose a targeted intelligent optimization algorithm (named GOAS) that can adaptively generate the parity-check matrix according to different audio cover. The experimental results show that the proposed method outperforms the state-of-the-art adaptive steganography with reduced embedding changes and improved audio quality while ensuring the ability against steganalysis.

In this paper, we propose a good decoding performance, low-complexity, and high-speed decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum-product decoding scheme. To reduce implementation complexity and hardware resource consumption, the messages in the iteration process are uniformly quantified and the function $\Psi (x)$ is approximated with second-order functions. The decoder architecture improves the decoding throughput by using partial parallel and pipeline structures. A modified construction method of parity check matrices was applied to prevent read&write conflicts and achieve high-speed pipeline structure. The simulation results show that our decoder architecture has good performance at signal-to-noise ratios (SNRs) as low as −0.6 dB. We have implemented our decoder architecture on a Virtex-7 XC7VX690T field programmable gate array (FPGA) device. The implementation results show that the FPGA-based LDPC decoder can achieve throughputs of 108.64 Mb/s and 70.32 Mb/s at SNR of 1.0 dB when the code length is 262,144 and 349,952, respectively. The decoder can find useful applications in those scenarios that require very low SNRs and high throughputs, such as the information reconciliation of continuous-variable quantum key distribution.

Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%–109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.

Belief propagation (BP) is a soft-decision (SD) decoder that is commonly used to obtain near-optimal decoding performance for linear codes defined over sparse parity-check matrix. Nevertheless, the BP yields poor performance when used in the decoding of algebraic block codes, usually described by a dense parity-check matrix. Hence, enhanced BP decoders transform the parity check matrix of such codes at each iteration for efficient decoding. In this article, the performance of the transformed parity-check matrix of the iterative SD decoder is analysed for the class of binary cyclic codes using a perfect knowledge model (PKM). The PKM computes a list of candidate matrices and selects a baseline parity-check matrix according to a distance metric. The selected matrix is optimal since it minimizes the probability of error over various choices in the list. Results show that, for a given channel condition, the conventional transformed matrix obtained by Gaussian elimination is sub-optimal and does not necessarily contain unitary weighted columns at corresponding columns of the unreliable bits. Moreover, PKM can be used to verify the performances of newly developed iterative SD decoders for binary cyclic codes based on parity-check equations instead of maximum-likelihood decoding.

The manuscript presents the construction of a diagonally structured Parity check matrix using lower and upper (LU) decomposition for regular Quasi Cyclic-Low Density Parity Check Codes (QC-LDPC) with girth 12. This diagonally structured parity check matrix reduces the sparsity characteristics of QC-LDPC codes. The regular Quasi Cyclic-LDPC code has been constructed using circulant shifting and randomization method in which uniform distribution of non-zero elements, XOR operation, and pairing of row and column has been done. A Simplified Log Domain Sum-Product Algorithm (SLDSPA) is used for the decoding of the constructed code. To reduce the CPU run time of the constructed code, a column-wise loop optimization technique is applied. The frame error rate and CPU run time is calculated for different code lengths such as code1 (816, 408), code2 (1008, 504), code3 (1032, 516), code4 (1944, 972), code5 (672, 336) and code6 (504, 252). The construction of regular QC-LDPC codes on half code rate is obtained for the weight of each row is 6 and each column is given by 3. The results showing that the constructed code is better performing in terms of Low FER (10−1 to 10−7), Low SNR (0 to 3.5 dB) and Less CPU run time in milliseconds.

Single bit errors occur more frequently in memory elements. So for the avoidance of these single bit errors the Hamming code technique was recognized as the best among all other coding techniques. The most effective coding technique was Hamming [16, 11, 5] 2 which results in single error detection and correction as well as double adjacent error detection and correction. In this paper, a method to design SEC-DAEC codes with optimized decoding is presented and evaluated. Extended Hamming code is developed by adding an extra parity bit. The implementation is evaluated and compared by its application in an audio signal authentication in matlab with introduced errors The evaluations show there is a slight increase in area, power and delay of the decoder.

Neural Normalized MinSum (N-NMS) decoding delivers better frame error rate (FER) performance on linear block codes than conventional normalized MinSum (NMS) by assigning dynamic multiplicative weights to each check-to-variable message in each iteration. Previous N-NMS efforts have primarily investigated short-length block codes (N < 1000), because the number of N-NMS parameters to be trained is proportional to the number of edges in the parity check matrix and the number of iterations, which imposes am impractical memory requirement when Pytorch or Tensorflow is used for training. This paper provides efficient approaches to training parameters of N-NMS that support N-NMS for longer block lengths. Specifically, this paper introduces a family of neural 2-dimensional normalized (N-2D-NMS) decoders with with various reduced parameter sets and shows how performance varies with the parameter set selected. The N-2D-NMS decoders share weights with respect to check node and/or variable node degree. Simulation results justify this approach, showing that the trained weights of N-NMS have a strong correlation to the check node degree, variable node degree, and iteration number. Further simulation results on the (3096,1032) protograph-based raptor-like (PBRL) code show that N-2D-NMS decoder can achieve the same FER as N-NMS with significantly fewer parameters required. The N-2D-NMS decoder for a (16200,7200) DVBS-2 standard LDPC code shows a lower error floor than belief propagation. Finally, a hybrid decoding structure combining a feedforward structure with a recurrent structure is proposed in this paper. The hybrid structure shows similar decoding performance to full feedforward structure, but requires significantly fewer parameters., This paper has been accepted by ISTC2021

This research was funded by AEI (https://doi.org/10.13039/501100011033 (accessed on 6 August 2021)), grant number PID2019-110525GB-I00., We design a decoding algorithm for linear codes over finite chain rings given by their parity check matrices. It is assumed that decoding algorithms over the residue field are known at each degree of the adic decomposition., PID2019-110525GB-I00

Previous studies revealed that low-density parity-check convolutional codes (LDPC-CC) with rational parity-check matrices may outperform LDPC-CC with ordinary polynomial parity-check matrices. However, such a performance improvement relies on a dynamic scheduling-aided decoding scheme with high processing latency which may prevent LDPC-CC with rational parity-check matrices from practical applications. In this paper, we find that conventional belief-propagation algorithms suitable for high-speed parallel implementation can still provide the satisfactory performance gain for LDPC-CC with rational parity-check matrices as long as some virtual channel outputs which can accelerate the convergence of iterative decoding are properly supplied. Criteria for generating virtual channel outputs are investigated from the viewpoint of Tanner graph. Simulation results are also provided for performance verification.

In recent years, there has been a growing interest in codes that can correct adjacent bit errors in memories. This is due to the increasing percentage of radiation induced errors that affect multiple cells due to technology scaling. The cells affected by the errors are physically close and in many cases adjacent. This means that in the absence of interleaving, adjacent bits will be likely to be affected by an error. A number of Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes have been proposed to deal with those errors. These codes have a low overhead in terms of number of additional parity check bits compared to Double Error Correction (DEC) codes. A problem is that they can introduce a significant penalty in terms of delay compared to a Single Error Correction (SEC) or a Single Error Correction and Double Error Detection (SEC-DED) code. This is due to the more complex decoding that needs to check approximately twice the number of syndrome patterns. In this paper, low delay SEC-DAEC codes are presented and the parity check matrices for 16, 32 and 64 bit data words are provided. To reduce the delay, a number of techniques are used in the construction of the code and in the implementation of the decoder. The evaluation shows that this results in significant savings compared to existing SEC-DAEC codes. Therefore, the proposed codes can be useful for high speed designs on which adjacent error correction is required.

This paper considers the problem of source coding with side information at the decoder, also called Slepian-Wolf source coding scheme. In practical applications of this coding scheme, the statistical relation between the source and the side information can vary from one data transmission to another, and there is a need to adapt the coding rate depending on the current statistical relation. In this paper, we propose a novel rate-adaptive code construction based on LDPC codes for the Slepian-Wolf source coding scheme. The proposed code design method allows to optimize the code degree distributions at all the considered rates, while minimizing the amount of short cycles in the parity check matrices at all rates. Simulation results show that the proposed method greatly reduces the source coding rate compared to the standard LDPCA solution., Comment: 25 pages, 7 figures, submitted to IEEE Transactions on Communications

The increasing importance of Multiple Cell Upsets (MCUs) in modern memories has spurred research on error correction codes that can correct adjacent bit errors. For example, Double Adjacent Error Correction (DAEC), 3-bit burst and 4-bit burst codes have been proposed in the last years. However, as the error correction capabilities are increased so is the complexity of the encoder and decoder circuits. This directly impacts the encoding and decoding delay and thus limits the use of the codes in high speed memories. To reduce the complexity, some techniques have been proposed recently. Those include more advanced optimization programs to find codes with a lower number of ones in the parity check matrix or the interleaving of data and parity check bits to simplify the decoding. In this paper, those techniques are combined to design more efficient 3-bit burst error correction codes. The encoders and decoders for the proposed codes have been implemented and compared with the state of the art 3-bit burst error correction codes. The results show that the new codes reduce the encoder and decoder delay significantly. Therefore, the proposed codes provide memory designers with a more efficient option to implement protection against 3-bit burst errors for high speed memories.

In this paper, a (21150, 19050) globally-coupled low-density parity check (GC-LDPC) code designed for NAND flash memories is presented. The proposed LDPC code comprises three disjoint subcodes which can be decoded independently. This highly structural parity check matrix contributes to efficient decoder implementation and flexible decoding flow control. Moreover, a two-phase local/global decoding procedure optimized for the proposed GC-LDPC code is introduced. Scenarios of collaborative decoding that leverages the special code structures are discussed. In the proposed decoder architecture, the pipelined processing elements with scheduling are employed to reduce the critical path and decoding latency as well. Implemented in UMC 65 nm process, the post-layout simulation shows a maximum decoding throughput of 4.32 Gb/s with the chip area 3.376 mm2.

This work proposes a new code which can be considered as the modification of linear block code with code rate 1/2 and less than 1/2. The theme of the work is derived from the controllability of discrete time system and accordingly the generator matrix is chosen. A procedure is proposed in this paper which can transform the lower dimensional space to higher dimensional space. A Code is subspace of a space, so, with the help of addition of an equivalent identity matrix, between I (Identity matrix) and P (Parity Check) matrix of the established generator matrix, the lower dimensional space is transformed to higher dimensional space. Multiple numbers of errors could be corrected with the help of this designed code. It is also shown that decoding of this code can be established using the methods like syndrome detection and nearest neighbor decoding. The proposed code satisfies all the bounds. The minimum distance d, which could be achieved here, is at least equal to the total no. of information bits wh...

When the proton released due to the decay of radioactive atoms in the chip, strikes the memory, the contents in cell can be altered resulting in soft errors. This phenomenon can be even caused by cosmic rays. As the spacing between the cells is decreasing in the CMOS technology, multiple nearby cells get affected due to radiations. In this work, detection and correction mechanism using H-Matrix for multiple possibilities of double adjacent errors is presented. When 32-data bits are considered, correction of double adjacent errors up to 8 bits are correctable. Double adjacent means two burst errors each with maximum 4 error bits. Using three different parity check matrices, three different H-Matrix based codes with different numbers of parity bits are proposed and comparatively analysed for different parameters.

Day by day the internet traffic is increasing rapidly. Challenges to improve these internet traffic requirements leads to evolution of 5G NR LDPC (New Radio Low Density Parity Check) codes which provides high coding gain and energy efficiency. BER Vs Eb/No dB curve defines the energy efficiency and coding gain of the any error correcting codes. LDPC codes which are adopted by 5G Standard are called 5G NR LDPC codes.In the design of the decoder,Message Passing Approach reduces the decoding complexiyt due to the sparsity of the parity check matrix.. An efficient decoding algorithm is the key to the successful code. In this paper an iterative minsum approximation message passing decoding algorithm has been implemented for both BG1 and BG2. Results show that the coding gain can be improved up to 9dB.

A new algorithm for efficient exact maximum likelihood decoding of polar codes (which may be CRC augmented), transmitted over the binary erasure channel, is presented. The algorithm applies a matrix triangulation process on a sparse polar code parity check matrix, followed by solving a small size linear system over GF(2). To implement the matrix triangulation, we apply belief propagation decoding type operations. We also indicate how this decoder can be implemented in parallel for low latency decoding. Numerical simulations are used to evaluate the performance and computational complexity of the new algorithm., Comment: Accepted to ISIT 2021

The main aim of this paper is to study various properties of extended binary Golay [24, 12, 8] code, when we know its generator matrix. Using MATLAB, we can study syndrome decoding, weight of a codeword, error correction and error detection of extended binary Golay [24, 12, 8] code.

The main aim of this paper is to study the encoding process of binary Schubert code [43,7] using MATLAB, when one knows its generator matrix. Using MATLAB, we can study syndrome decoding, weight of a codeword, error correction and error detection of the code.

The main aim of this paper is to study various properties of extended binary Hamming [8, 4, 4] code, when we know its generator matrix. Using MATLAB, we can study syndrome decoding, weight of a codeword, error correction and error detection of binary Hamming [8, 4, 4] code.

A new class of convolutional codes, called skew convolutional codes, that extends the class of classical fixed convolutional codes, is proposed. Skew convolutional codes can be represented as periodic time-varying convolutional codes but have a description as compact as fixed convolutional codes. Designs of generator and parity check matrices, encoders, and code trellises for skew convolutional codes and their duals are shown. For memoryless channels, one can apply Viterbi or BCJR decoding algorithms, or a dualized BCJR algorithm, to decode skew convolutional codes.

The Low Density Parity Check (LDPC) codes are linear block codes, which are Shannon Limit codes. These codes are attained least error floors of data bits for data transfer applications used in communication systems. However, the proposed LDPC codes are more beneficial than Turbo codes because of reduction in the decoding complexity and detection of the errors in less cycle time. This results the reduction of decoding time, low decoding latency and as well as least error floors in communication, when the transmitted data contains multiple error bits. This paper is proposed to represent the majority logic decoding/detecting of LDPC codes. This paper proposes the Generation of Generator and Parity Check matrices for both Binary and Non-Binary LDPC Codes. Here, the proposed Majority Logic Decoder/Detector (MLDD) is Hard decision decrypting scheme and it uses majority logic decoding based on the data transmission and reception in communication channel. This paper also elaborates the effective implementation of encoding and decoding of LDPC Codes.

Quantum low-density generator matrix (QLDGM) codes based on Calderbank-Steane-Shor (CSS) constructions have shown unprecedented error correction capabilities, displaying much improved performance in comparison to other sparse-graph codes. However, the nature of CSS designs and the manner in which they must be decoded limit the performance that is attainable with codes that are based on this construction. This motivates the search for quantum code design strategies capable of avoiding the drawbacks associated with CSS codes. In this article, we introduce non-CSS quantum code constructions based on classical LDGM codes. The proposed codes are derived from CSS QLDGM designs by performing specific row operations on their quantum parity check matrices to modify the associated decoding graphs. The application of this method results in performance improvements in comparison to CSS QLDGM codes, while also allowing for greater flexibility in the design process. The proposed non-CSS QLDGM scheme outperforms the best quantum low-density parity check codes that have appeared in the literature.

The notion of Generalized Hamming weights of block codes has been investigated since the nineties due to its significant role in coding theory and cryptography. In this paper we extend this concept to the context of convolutional codes. In particular, we focus on column distances and introduce the novel notion of generalized column distances (GCD). We first show that the hierarchy of GCD is strictly increasing. We then provide characterizations of such distances in terms of the truncated parity-check matrix of the code, that will allow us to determine their values. Finally, the case in which the parity-check matrix is in systematic form is treated. This work was supported in part by the Sao Paulo Research Foundation (FAPESP) under Grant 2013/25977-7. The work of Sara D. Cardell was supported in part by the FAPESP, under Grant 2015/07246-0 and in part by the CAPES. The work of Marcelo Firer was supported in part by the CNPq. The work of Diego Napp was supported in part by the Spanish, Generalitat Valenciana, Univesitat d’Alacant, under Grant AICO/2017/128 and Grant VIGROB-287.

The paper presents the results of developing a decoder architecture of low-density parity check code of the DVB-S2 standard for field programmable gate array. It supports several code rates and codeword lengths described in the appendix of the standard. The proposed decoder architecture has a partially parallel structure, which allows to achieve high decoding performance and efficient use of chip area. The presence of double-diagonal submatrices in the structure of the parity check matrices was also confirmed, and a method for eliminating them was implemented. In the work, an analysis of parameters affecting the static and dynamic power consumption in the field programmable gate array was made. Based on it, algorithmic and architectural methods for reducing consumption are proposed. The paper describes the developed architectures and methods to reduce chip power consumption.

This paper proposes the use of systematic LDPC codes for hard decision Message Passing (hMP), which is a predecoder to Vector Symbol Decoding (VSD) for non-binary codes. VSD is a verification-based decoder whose outputs are decoded code words. LDPC are randomly generated and by nature, they are non-systematic codes. Using systematic instead of non-systematic codes allows the decoder to obtain the decoded data directly without a troublesome mapping step. In the simulations, 15 regular parity check matrices H are randomly generated and converted to their systematic forms. Results in a Gilbert-Elliot 2-state fading channel model with 6 different channel conditions show that hMP prefers codes with lower- weight H. For column weight of 9 bits and row weight of 18 bits, systematic H have lower weight after row operation and are better than the non-systematic ones for all channel conditions.

The communication method conveys information from the transmitter to the receiver over an intermediate medium. The competence of received information is determined by medium and clatter. There is a great need for robust error correction techniques with ever accumulative usage of wireless expedients such as portable electronic items and broadband modems. Wireless communication schemes depend on advanced error rectification techniques for their suitable functioning. Hence transferring and getting information with less or without error, while utilizing the accessible bandwidth is a foremost proposal, project necessities for present digital wireless communication systems comprising of high throughput, low power consumption, and less area. In this article, the functional analysis is performed for error control coding technique i.e., Low-Density-Parity-Check (LDPC) coding in terms of device utilization and power. The functional verification and the simulation are performed using Verilog HDL. Error correction techniques such as Linear block codes, RS codes, Convolutional codes are employed to implement forward error correction but as the constraint length increases the design of decoders becomes more complex. LDPC is a type of block code that is capable of correcting random errors. They are popular because of their eminent detection and correction capabilities. LDPC encoding technique provides high throughput and aims to improve BER when compared to conventional techniques. The decoding of LDPC codeword employs the Message Passing Algorithm, where each bit in a codeword is allocated to special nodes. The performance of these codes is hence better and easily attains Shannon’s limit than the previously used codes. Synthesis for the technique is performed and utilization reports are derived from the synthesis in Vivado.

Code-based public key cryptosystems have been found to be an interesting option in the area of Post-Quantum Cryptography. In this work, we present a key encapsulation mechanism (KEM) using a parity check matrix of the Generalized Srivastava code as the public key matrix. Generalized Srivastava codes are privileged with the decoding technique of Alternant codes as they belong to the family of Alternant codes. We exploit the dyadic structure of the parity check matrix to reduce the storage of the public key. Our encapsulation leads to a shorter ciphertext as compared to DAGS proposed by Banegas et al. in Journal of Mathematical Cryptology which also uses Generalized Srivastava code. Our KEM provides IND-CCA security in the random oracle model. Also, our scheme can be shown to achieve post-quantum security in the quantum random oracle model.

In this chapter, we will explain the construction of linear block codes. Since linear block codes are vector subspaces, we advise to the reader to study Chap. 1 before proceeding to Chap. 2. Without the knowledge of basic concepts of linear algebra, such as groups, fields, vector spaces, and subspaces, it is difficult to comprehend the philosophy behind the concept of linear block codes. We advise the reader to study the section related to the philosophy of channel encoding before studying the sections related to the encoding and decoding operations. We explain the purpose of channel encoding in Sect. 2.5. After introducing the construction of linear block codes, we explain the encoding operation and give some fundamental definitions such as minimum distance, generator matrix, and parity check matrix. In sequel, we explain equivalent codes, error detection and correction capability of linear block codes, and Hamming spheres.

In this chapter, we will first explain the decoding of linear block codes using syndrome tables, then provide information about some well-known preliminary binary linear block codes. Syndrome decoding is a preliminary decoding approach; most of the modern decoding techniques do not employ syndrome decoding. However, to comprehend the decoding logic of linear block codes, it is essential to understand the syndrome decoding operation. For this purpose, we first explain the construction of standard arrays and decoding operation using standard arrays. Syndromes are nothing but concise representation of standard arrays. After standard arrays, we explain the syndrome decoding concept. Following the explanation of the syndrome decoding, we introduce some linear block codes well-known in the literature, such as Golay code, Reed-Muller codes, and Hamming codes, and discuss the error correction capability and decoding operations of these linear block codes. Non-systematic forms of the generator and parity check matrices of the Hamming codes are also explained.

Error correction is a significant step in postprocessing of continuous-variable quantum key distribution system, which is used to make two distant legitimate parties share identical corrected keys. We propose an experiment demonstration of high speed error correction with multi-edge type low-density parity check (MET-LDPC) codes based on graphic processing unit (GPU). GPU supports to calculate the messages of MET-LDPC codes simultaneously and decode multiple codewords in parallel. We optimize the memory structure of parity check matrix and the belief propagation decoding algorithm to reduce computational complexity. Our results show that GPU-based decoding algorithm greatly improves the error correction speed. For the three typical code rate, i.e., 0.1, 0.05 and 0.02, when the block length is $10^6$ and the iteration number are 100, 150 and 200, the average error correction speed can be respectively achieved to 30.39Mbits/s (over three times faster than previous demonstrations), 21.23Mbits/s and 16.41Mbits/s with 64 codewords decoding in parallel, which supports high-speed real-time continuous-variable quantum key distribution system., 8 pages, 2 figures

This paper presents a novel linear error detection and correction approach for single and multiple bit error codes called low complexity parity check (LCPC) code. The LCPC code detects and corrects consecutive and non-consecutive bit errors. It can be used as a forward error correction scheme in the data transmission system of green wireless networks and the green Internet of Things. The proposed code improves network performance in terms of throughput, end-to-end delay, and bit error rate (BER). LCPC codes also have less complexity and lower memory requirements than Reed Solomon (RS) and low-density parity check (LDPC) codes because they have less non-zero elements in the generator matrix and the parity check matrix. Unlike LDPC codes, LCPC codes do not require reiteration in the decoding process. Various code rates of the LCPC code are proposed to reduce the complexity of the encoding and decoding process, which in turn decreases energy consumption. Simulation results show that the proposed LCPC (9, 4) code outperforms the popular LDPC codes. Compared with the LDPC (8, 4) with the decode bit flip algorithm, LCPC (9, 4) offers a coding gain of nearly 3 dB at a BER equal to 10−5.

Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings, have raised significant concerns in its real applications. Recent studies even show that the common memory error repair “remedies” cannot efficiently address them. In this article, we for the first time systematically study the potentials of the strong low-density parity-check (LDPC) code for combating such unique asymmetric errors in both single-level-cell (SLC) and multi-level-cell (MLC) STT-RAM designs. A generic STT-RAM channel model suitable for the SLC/MLC designs, is developed to analytically calibrate all the accumulated asymmetric factors of the write/read operations. The key initial information for LDPC decoding, namely asymmetric log-likelihood ratio (A-LLR), is redesigned and extracted from the proposed channel model, to unleash the LDPC’s asymmetric error correcting capability. LDPC codec is also carefully designed to lower the hardware cost by leveraging the systematic-structured parity check matrix. Then two customized short-length LDPC codes—(585,512) and (683,512)—augmented from the semi-random parity check matrix and the A-LLR based asymmetric decoding, are proposed for SLC and MLC STT-RAM designs, respectively. Experiments show that our proposed LDPC designs can improve the STT-RAM reliability by at least 10 2 (10 4 ) when compared to the existing error correction codes (ECCs) for the SLC (MLC) design, demonstrating the feasibility of LDPC solutions on STT-RAM.

In this paper, we propose a generalized minimum-sum decoding algorithm using a linear approximation (LAMS) for protograph-based low-density parity-check (PB-LDPC) codes with quasi-cyclic (QC) structures. The linear approximation introduces some factors in each decoding iteration, which linearly adjust the check node updating and channel output. These factors are optimized iteratively using machine learning, where the optimization can be efficiently solved by a small and shallow neural network with training data produced by the LAMS decoder. The neural network is built according to the parity check matrix of a PB-LDPC code with a QC structure which can greatly reduce the size of the neural network. Since, we optimize the factors once per decoding iteration, the optimization is not limited by the number of the iterations. Then, we give the optimized results of the factors in the LAMS decoder and perform decoding simulations for PB-LDPC codes in fifth generation mobile networks (5G). In the simulations, the LAMS algorithm shows noticeable improvement over the normalized and the offset minimum-sum algorithms and even better performance than the belief propagation algorithm in some high signal-to-noise ratio regions.

In this paper, we design an irregular low-density parity-check (LDPC) codes for unequal inter-symbol interference channels based on the modified extrinsic information transfer chart. During transmission, each LDPC codeword will be divided and transmitted to the different channels. The aim of this scheme is to avoid transmitting the whole codeword in a high error rate channel. The simulation results show that the proposed code optimized for both PR1 and PR2 channels can achieve a 0.2 coding gain over the codes designed specifically for each individual channel. When this simple code is applied to a perpendicular channel with these two targets, the coding gains of the proposed code is about 0.08 dB at the frame error rate of $10^{-3}$ .

The key challenges in real time voice communication in long term evolution mobile are reduction in complexity and latency. Efficient encoding and decoding algorithms can cater to these. The implementation of such polar code based efficient algorithms is proposed in this paper. The overall latency of 3.8 ms is needed to process 8 bit block length. The novel sub-matrix near to identity matrix is presented. This resulted into minimization of loops among least reliable bits due to iterated parity check matrix. Look-up table based memory mapping is used in encoder to reduce latency while Euclidian decoding technique is used in decoder. The number of iterations is reduced by 50%. The experimentation is performed with additive white Gaussian noise and QPSK modulation. The proposed modified iterative decoding algorithm requires SNR of 5.5 dB and 192 computations for targeted bit error rate of 10−4. The second proposed method needs 9 dB, 2 iterations for 384 computations. The penalty paid is quantization error of 0.63% due to restricting computations to fourth order series of hyperbolic function with same 8 bit block length.

In this paper, we discuss the belief propagation (BP) decoding of polar codes. The performance of polar codes for short lengths is not satisfactory. Therefore, motivated by this we propose a novel technique to improve the performance of polar codes under BP decoding. In order to enhance the reliability of the variable nodes’ propagated messages in BP decoding, the messages are multiplied by previous messages of variable nodes. It is also shown that the BP decoding can be performed on polar codes if the factor graph is constructed according to the parity check matrix of polar codes. Simulation results in binary-input additive white Gaussian noise channel show that using the proposed method a gain of 1–2 dB can be achieved. We also show that the complexity of proposed decoder is same as the complexity of standard BP decoder. Furthermore, we show that the proposed decoder requires about 10–25 iterations less than the standard BP decoder.

The LDPC codes are Shannon Limit codes that can achieve low bit error rates for SNR applications. The features of LDPC Codes are reduction in the decoding time, latency and as well as no error-floors at high SNRs. The proposed algorithms are SBF, MSA, and MLDD. The various decoding algorithms have been compared for these codes. The parameters are describing the which algorithm further helps in selecting the better decoder used for Medical and Signal Processing Applications. These codes are also used in Generating the Barcodes depends on the size of the Parity Check matrix.

For correcting burst errors in channels with memory are widely used various code constructions together with interleaving. For increasing the reliability of information transmission in such channels is advisable to apply algebraic interleaved convolutional codes. The principles of polynomial and matrix representation of algebraic interleaved convolutional codes with predetermined coding rate are given. The parameters of these codes which completely determined by the modified generator polynomial are presented. Algebraic decoding these codes has been a large computational complexity and limited correction capability. Algebraic interleaved convolutional codes can be represented as a long binary block codes which can be determined with using generator or parity check matrix. The combination approach to iterative decoding these codes whose purpose is to find the most probable codeword by assessing a log likelihood ratio of each code symbol is proposed. The share using information about the reliability of symbols, adaptive belief propagation and natural computing procedures are offered. According to this approach each iteration of decoding starts with finding the expected codeword using natural computing procedures. If the received vector is not codeword, then adaptive belief propagation procedures are used for updating the information about the reliability of symbols which then used in the next iteration of decoding. The basic principles of implementation of the main steps of the proposed method decoding algebraic interleaving convolution codes are presented.

An improved extension method based on protograph extrinsic information transfer (PEXIT) charts is proposed to design rate-compatible quasi-cyclic low-density parity-check (QC-LDPC) codes with more flexible rates and better performance. The masking matrix of the highest-rate code can first be constructed column by column to own the lowest decoding threshold. Then, an extension algorithm is proposed to obtain the masking matrices of lower-rate codes with flexible rates. Finally, the base matrices with small amount of short cycles are designed and the parity-check matrices of rate-compatible QC-LDPC codes are obtained through matrix extension. Simulations show that compared with the existing codes, the proposed codes have more flexible rates while achieving better performance.

Most of cryptosystems, identification and signature schemes rely on the discrete logarithm problem and the prime factorization problem. These problems would be broken through Shor's quantum factorization algorithm in the case that quantum computers would come to exist. Code-based cryptography is one of post-quantum cryptography. There are several cryptography to reduce the key size by using the public matrix with the circulant structure, but some attacks have been proposed with the circulant structure as a weak point. In this paper, we propose a code-based identification scheme using high-density parity-check (HDPC) matrices. The poposed scheme is an improvement of Stern's identification scheme based on the binary syndrome decoding (BSD) problem. In the proposed scheme, we apply HDPC matrices to the BSD problem in order to prevent attacks using iterative decoding algorithm. Also, to prevent attack using circulant structure, we construct HDPC matrices of multiple block-row with circulant submatrices of different size. Furthermore, we evaluate the security level, key size, computational cost and security against existing attacks.

Recent developments in the field of deep learning have motivated many researchers to apply these methods to problems in quantum information. Torlai and Melko first proposed a decoder for surface codes based on neural networks. Since then, many other researchers have applied neural networks to study a variety of problems in the context of decoding. An important development in this regard was due to Varsamopoulos et al. who proposed a two-step decoder using neural networks. Subsequent work of Maskara et al. used the same concept for decoding for various noise models. We propose a similar two-step neural decoder using inverse parity-check matrix for topological color codes. We show that it outperforms the state-of-the-art performance of non-neural decoders for independent Pauli errors noise model on a 2D hexagonal color code. Our final decoder is independent of the noise model and achieves a threshold of $10 \%$. Our result is comparable to the recent work on neural decoder for quantum error correction by Maskara et al.. It appears that our decoder has significant advantages with respect to training cost and complexity of the network for higher lengths when compared to that of Maskara et al.. Our proposed method can also be extended to arbitrary dimension and other stabilizer codes., Comment: 12 pages, 12 figures, 2 tables, submitted to the 2019 IEEE International Symposium on Information Theory

In this paper, we design and develop a new class of linear algebraic codes defined as soft linear algebraic codes using soft sets. The advantage of using these codes is that they have the ability to transmit m-distinct messages to m-set of receivers simultaneously. The methods of generating and decoding these new classes of soft linear algebraic codes have been developed. The notion of soft canonical generator matrix, soft canonical parity check matrix, and soft syndrome are defined to aid in construction and decoding of these codes. Error detection and correction of these codes are developed and illustrated by an example.

In large scale distributed systems such as cloud storage systems, erasure coding is a fundamental technique to provide high reliability at low monetary cost. Compared with the traditional disk arrays, cloud storage systems use an erasure coding scheme with both flexible fault tolerance and high scalability. Thus, Reed-Solomon (RS) Codes or RS-based codes are popular choices for cloud storage systems. However, the decoding performance for RS-based codes is not as good as XOR-based codes, which are optimized via investigating the relationships among different parity chains or reducing the computational complexity of matrix multiplications. Therefore, exploring an efficient decoding method is highly desired. To address the above problem, in this paper, we propose an Advanced Parity-Check Matrix (APCM) based approach, which is extended from the original Parity-Check Matrix based (PCM) approach. Instead of improving the decoding performance of XOR-based codes in PCM, APCM focuses on optimizing the decoding efficiency for RS-based codes. Furthermore, APCM avoids the matrix inversion computations and reduces the computational complexity of the decoding process. To demonstrate the effectiveness of the APCM, we conduct intensive experiments by using both RS-based and XOR-based codes under cloud storage environment. The results show that, compared to typical decoding methods, APCM improves the decoding speed by up to 32.31% in the Alibaba cloud storage system.

Non-binary low-density parity-check (NB-LDPC) codes exhibit a much better performance than their binary counterparts, especially for moderate codeword length and high-order modulation. However, their decoding algorithms suffer from very high computational complexity. In this paper, a low-complexity algorithm is proposed, named parity-check erased algorithm (PCEA), where an additional parity check bit is added to each symbol of the codeword when encoding and a series of simple operations are performed based on these bits during decoding. As a universal joint coding and decoding algorithm, the PCEA can be combined with arbitrary NB-LDPC encoding schemes and decoding algorithms based on message passing. The proposed algorithm facilitates significant improvement of decoding performance with a small decrease of the code rate. Additionally, it usually has an even better performance than a nearly same-rate code constructed by the original method, and requires much lower decoding complexity due to smaller size of the parity check matrix.

This paper presents hardware-friendly LDPC decoding schedules for 5G hybrid automatic repeat request (HARQ) applications. Since there are built-in punctured blocks in the parity check matrix (PCM), a scheduling technique is proposed that allows the punctured nodes to be efficiently recovered. For HARQ using the Chase combining (CC), the previous decoding results corresponding to the punctured part are retained, and the proposed layered decoding is arranged according to the row weight. For HARQ using the incremental redundancy (IR) approach, the parity bits corresponding to the pure-row-orthogonal part of the PCM are transmitted first. The hardware implementation shows that the throughput can be increased by 21.37% for the first decoding attempt, 56.9% for CC-HARQ and 14.51% for IR-HARQ when the code rate reaches 0.303.

Error Correction Codes (ECCs) are commonly used to protect memories against soft errors with an impact on memory area and delay. For large memories, the area overhead is mostly due to the additional cells needed to store the parity check bits. In terms of delay, the overhead is mostly needed to detect and correct errors when the data is read from the memory. Most ECCs that can correct more than one error have a complex decoding process and so are limited in high speed memory applications. One exception is One Step Majority Logic Decodable (OS-MLD) codes for which decoding can be done in parallel at high speed. Unfortunately, there are only a few OS-MLD codes that provide a limited choice in terms of block sizes, error correction capabilities and code rate. Therefore, there is considerable interest in a novel construction of OS-MLD codes to provide additional choices for protecting memories. In this paper, a new method to construct Double Error Correction (DEC) OS-MLD codes is presented. This method is based on the use of parity check matrices in which two bits have at most two parity check equations in common; the proposed method provides codes that require a smaller number of parity check bits than existing codes like Orthogonal Latin Square (OLS) codes. The drawback of the proposed Two Bit Overlap (TBO) codes is that they require slightly more complex decoding than OLS codes. Therefore, they provide an intermediate solution between OLS and non OS-MLD codes in terms of decoding delay and number of parity check bits. The proposed TBO codes have been implemented for some block sizes and compared to both OLS and BCH codes to illustrate the trade off in delay and memory overhead. Finally, this paper discusses the generalization of the proposed scheme to codes with larger error correction capabilities. Publicado