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We consider in this letter the problem of blind frame synchronization of Low Density Parity-Check (LDPC) codes. We present and compare new methods of blind frame synchronization based on the calculation of Likelihood functions of the syndrome. Simulation results show that the four proposed synchronization techniques are effective once applied to LDPC codes. The method that involves the maximization of the Likelihood Difference (LD) function of the parity-checks, presents the best results in terms of probability of false synchronization.

In his pioneering work on LDPC codes, Gallager dismissed codes with parity-check matrices of weight two after proving that their minimum Hamming distances grow at most logarithmically with their code lengths. In spite of their poor minimum Hamming distances, it is shown that quasi-cyclic LDPC codes with parity-check matrices of column weight two have good capability to correct phased bursts of erasures which may not be surpassed by using quasi-cyclic LDPC codes with parity-check matrices of column weight three or more. By modifying the parity-check matrices of column weight two and globally coupling them, the erasure correcting capability can be further enhanced. Quasi-cyclic LDPC codes with parity-check matrices of column weight three or more that can correct phased bursts of erasures and perform well over the AWGN channel are also considered. Examples of such codes based on Reed-Solomon and Gabidulin codes are presented.

An efficient compact encoding process with the pipelining design of Low Density Parity Check (LDPC) Encoder with a two stage, three stage and Maximal Rate Pipelining (MRP) structures are proposed in this work. Comparatively, LDPC encoding is more complex than decoding. The complexity mainly referred to the mathematical computation involved in the design of LDPC encoder. There are several methods used to design reduced parity check matrix, one of the methods involved is the Gauss Elimination method. Conventional and wave pipelining techniques are implemented to overcome the disadvantages of the area, latency, etc., The designed architectures are synthesized in SYNOPSYS tool and implemented in the XC3S-250E FPGA device. The overheads like power and area are efficiently reduced by wave pipelining and their efficiency can be proved by synthesis report. This showcases that the LDPC Encoders require less memory by using MRP structure.

Syndrome-Trellis Code (STC) is a near-optimal convolutional method for adaptive steganography. Hitherto, the existing adaptive steganography commonly depends on the carefully designed distortion cost function, which controls the embedding position of the message in the cover signal. From another point of view, we implement adaptive steganography by improving the STC coding process (named Adaptive-STC). The parity-check matrix is the key to the encoding and extraction process of STC. In this work, we prove that the average embedding change probability of corresponding elements can be changed by adjusting its submatrix. Following that, we specially design an adaptive parity-check matrix to replace the designed distortion cost to restrict the embedding position. The generation of the adaptive parity-check matrix can be formulated as a multi-constrained integer programming problem in which the width of the submatrix is allocated at a fixed height. To solve this particular problem, we propose a targeted intelligent optimization algorithm (named GOAS) that can adaptively generate the parity-check matrix according to different audio cover. The experimental results show that the proposed method outperforms the state-of-the-art adaptive steganography with reduced embedding changes and improved audio quality while ensuring the ability against steganalysis.

In this paper, we propose a good decoding performance, low-complexity, and high-speed decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum-product decoding scheme. To reduce implementation complexity and hardware resource consumption, the messages in the iteration process are uniformly quantified and the function $\Psi (x)$ is approximated with second-order functions. The decoder architecture improves the decoding throughput by using partial parallel and pipeline structures. A modified construction method of parity check matrices was applied to prevent read&write conflicts and achieve high-speed pipeline structure. The simulation results show that our decoder architecture has good performance at signal-to-noise ratios (SNRs) as low as −0.6 dB. We have implemented our decoder architecture on a Virtex-7 XC7VX690T field programmable gate array (FPGA) device. The implementation results show that the FPGA-based LDPC decoder can achieve throughputs of 108.64 Mb/s and 70.32 Mb/s at SNR of 1.0 dB when the code length is 262,144 and 349,952, respectively. The decoder can find useful applications in those scenarios that require very low SNRs and high throughputs, such as the information reconciliation of continuous-variable quantum key distribution.

Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%–109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.

Belief propagation (BP) is a soft-decision (SD) decoder that is commonly used to obtain near-optimal decoding performance for linear codes defined over sparse parity-check matrix. Nevertheless, the BP yields poor performance when used in the decoding of algebraic block codes, usually described by a dense parity-check matrix. Hence, enhanced BP decoders transform the parity check matrix of such codes at each iteration for efficient decoding. In this article, the performance of the transformed parity-check matrix of the iterative SD decoder is analysed for the class of binary cyclic codes using a perfect knowledge model (PKM). The PKM computes a list of candidate matrices and selects a baseline parity-check matrix according to a distance metric. The selected matrix is optimal since it minimizes the probability of error over various choices in the list. Results show that, for a given channel condition, the conventional transformed matrix obtained by Gaussian elimination is sub-optimal and does not necessarily contain unitary weighted columns at corresponding columns of the unreliable bits. Moreover, PKM can be used to verify the performances of newly developed iterative SD decoders for binary cyclic codes based on parity-check equations instead of maximum-likelihood decoding.

This paper proposes an algorithm to design rate-adaptive irregular LDPC codes with improved Bit error rate (BER) performance. It focuses on achieving better BER results for higher order coding rates which are in high demand for 5G mobile communications. The algorithm generates a parity check matrix based on the message block size. The encoding complexity of the irregular LDPC code is comparatively reduced due to the proposed parity check matrix. Simulation results compare the BER performances of irregular LDPC codes for various code rates and modulation schemes with the Parity check matrix (PCM) generated by the proposed algorithm. The BER performance of improved irregular LDPC code is analyzed in a real-time scenario using Software Defined Radio platform as well.

This research was funded by AEI (https://doi.org/10.13039/501100011033 (accessed on 6 August 2021)), grant number PID2019-110525GB-I00., We design a decoding algorithm for linear codes over finite chain rings given by their parity check matrices. It is assumed that decoding algorithms over the residue field are known at each degree of the adic decomposition., PID2019-110525GB-I00

Previous studies revealed that low-density parity-check convolutional codes (LDPC-CC) with rational parity-check matrices may outperform LDPC-CC with ordinary polynomial parity-check matrices. However, such a performance improvement relies on a dynamic scheduling-aided decoding scheme with high processing latency which may prevent LDPC-CC with rational parity-check matrices from practical applications. In this paper, we find that conventional belief-propagation algorithms suitable for high-speed parallel implementation can still provide the satisfactory performance gain for LDPC-CC with rational parity-check matrices as long as some virtual channel outputs which can accelerate the convergence of iterative decoding are properly supplied. Criteria for generating virtual channel outputs are investigated from the viewpoint of Tanner graph. Simulation results are also provided for performance verification.

Field-programmable gate array are frequently used to implement high-speed Low-density Parity-check (LDPC) decoders. The conventional practice is to develop a register transfer level (RTL) description of a digital circuit, which requires considerable simulation and verification, resulting in a long development cycle. High-level synthesis (HLS) tools significantly accelerate the hardware design process by using software programming languages such as C/C++. Well optimized code can be synthesized by the HLS tools into efficient hardware circuits. In this paper, we designed a Xilinx FPGA-based LDPC decoder using Vivado HLS. The decoder takes advantage of the cyclic shift of the submatrix in the parity check matrix of the quasi-cyclic LDPC (QC-LDPC) codes and uses a wide-pipeline architecture to process one row/column of all non-zero submatrices per clock cycle, with decoding throughput of hundreds of Mbps. By using different arrays to store data on multiple diagonals in a submatrix can easily avoid the performance bottleneck caused by access conflicts. In addition, the decoder has strong generality and flexibility, which has a high practical value.

This paper presents an enhanced partially-parallel low-density parity-check (LDPC) decoder based on Consultative Committee for Space Data Systems (CCSDS) standard for high speed near Earth applications. Architectural level optimization is exploited to reduce hardware complexity and increase decoding throughput. To enchance the parallelism of the partially-parallel decoder, high circulant weight submatrix of the parity check matrix (PCM) are partitioned into several identity matrices with corresponding cyclic-shifted value and processed separately. Furthermore, messages corresponding to adjacent rows of the cyclic-shifted identity matrix are stored in one memory entry, and low-complexity data aligners are designed between memories and processing units to avoid memory access conflicts. Hardware implementation of a (8176,7154) LDPC code on Xilinx Virtex-5 XC5VLX330 FPGA shows that the proposed decoder can achieve a decoding throughput of 1.02 Gb/s at 10 iterations.

This paper considers the problem of source coding with side information at the decoder, also called Slepian-Wolf source coding scheme. In practical applications of this coding scheme, the statistical relation between the source and the side information can vary from one data transmission to another, and there is a need to adapt the coding rate depending on the current statistical relation. In this paper, we propose a novel rate-adaptive code construction based on LDPC codes for the Slepian-Wolf source coding scheme. The proposed code design method allows to optimize the code degree distributions at all the considered rates, while minimizing the amount of short cycles in the parity check matrices at all rates. Simulation results show that the proposed method greatly reduces the source coding rate compared to the standard LDPCA solution., Comment: 25 pages, 7 figures, submitted to IEEE Transactions on Communications

The increasing importance of Multiple Cell Upsets (MCUs) in modern memories has spurred research on error correction codes that can correct adjacent bit errors. For example, Double Adjacent Error Correction (DAEC), 3-bit burst and 4-bit burst codes have been proposed in the last years. However, as the error correction capabilities are increased so is the complexity of the encoder and decoder circuits. This directly impacts the encoding and decoding delay and thus limits the use of the codes in high speed memories. To reduce the complexity, some techniques have been proposed recently. Those include more advanced optimization programs to find codes with a lower number of ones in the parity check matrix or the interleaving of data and parity check bits to simplify the decoding. In this paper, those techniques are combined to design more efficient 3-bit burst error correction codes. The encoders and decoders for the proposed codes have been implemented and compared with the state of the art 3-bit burst error correction codes. The results show that the new codes reduce the encoder and decoder delay significantly. Therefore, the proposed codes provide memory designers with a more efficient option to implement protection against 3-bit burst errors for high speed memories.

A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works.

In this paper, a (21150, 19050) globally-coupled low-density parity check (GC-LDPC) code designed for NAND flash memories is presented. The proposed LDPC code comprises three disjoint subcodes which can be decoded independently. This highly structural parity check matrix contributes to efficient decoder implementation and flexible decoding flow control. Moreover, a two-phase local/global decoding procedure optimized for the proposed GC-LDPC code is introduced. Scenarios of collaborative decoding that leverages the special code structures are discussed. In the proposed decoder architecture, the pipelined processing elements with scheduling are employed to reduce the critical path and decoding latency as well. Implemented in UMC 65 nm process, the post-layout simulation shows a maximum decoding throughput of 4.32 Gb/s with the chip area 3.376 mm2.

We develop a systematic theory for the construction of quantum codes from classical Reed–Solomon over $${\mathbb {F}}_{p^k}$$ , where p is prime and $$k \in {\mathbb {Z}}^{+}$$ . Based on two classical $$[n,n-d_m+1,d_m]$$ Reed–Solomon codes over $${\mathbb {F}}_{p^k}$$ , we provide the construction of an $$[[n,n+n_e-2(d_m-1),d_m]]$$ entanglement-assisted Reed–Solomon code over qudits of dimension $$d=p^k$$ that saturates the quantum Singleton bound and needs $$n_e$$ entangled qudits, which involves obtaining the explicit form of the stabilizers for the code. Our contributions towards the entanglement-assisted Reed–Solomon code are multi-fold as follows: (a) Based on the parity check matrices of the classical Reed–Solomon codes, the explicit form of the stabilizers of the entanglement-assisted Reed–Solomon code are provided and the rate-optimal code is obtained. (b) Based on the entanglement-assisted Reed–Solomon code, a burst error correcting code for qudits of dimension p that corrects a burst of $$k(t_m-1)$$ qudits or less, where $$t_m = \lfloor (d_m-1)/2\rfloor $$ is provided. (c) Finally, we provide amenable circuits for encoding and error correction with quantum circuit complexity of $${\mathcal {O}}(n^2)$$ , useful for practical implementations.

Day by day the internet traffic is increasing rapidly. Challenges to improve these internet traffic requirements leads to evolution of 5G NR LDPC (New Radio Low Density Parity Check) codes which provides high coding gain and energy efficiency. BER Vs Eb/No dB curve defines the energy efficiency and coding gain of the any error correcting codes. LDPC codes which are adopted by 5G Standard are called 5G NR LDPC codes.In the design of the decoder,Message Passing Approach reduces the decoding complexiyt due to the sparsity of the parity check matrix.. An efficient decoding algorithm is the key to the successful code. In this paper an iterative minsum approximation message passing decoding algorithm has been implemented for both BG1 and BG2. Results show that the coding gain can be improved up to 9dB.

A new algorithm for efficient exact maximum likelihood decoding of polar codes (which may be CRC augmented), transmitted over the binary erasure channel, is presented. The algorithm applies a matrix triangulation process on a sparse polar code parity check matrix, followed by solving a small size linear system over GF(2). To implement the matrix triangulation, we apply belief propagation decoding type operations. We also indicate how this decoder can be implemented in parallel for low latency decoding. Numerical simulations are used to evaluate the performance and computational complexity of the new algorithm., Comment: Accepted to ISIT 2021

The paper proposes hardware implementation of the LDPC decoder (Low Density Parity Check) as a serial architecture in the FPGA structure. The implemented decoder has 4-bit Log-Likelyhood Ratio messages precision and is dedicated for regular (3,6) code with 512 x 1024 parity check matrix. In order to reduce the complexity, the proposed decoder uses Min-Sum algorithm for check nodes (CNUs). In this article we present Bit Error Rate results that prove correctness of the decoder operation implemented in the Intel Cyclone IV. We also estimate power consumption of this implementation.

The main aim of this paper is to study the encoding process of binary Schubert code [43,7] using MATLAB, when one knows its generator matrix. Using MATLAB, we can study syndrome decoding, weight of a codeword, error correction and error detection of the code.

A new class of convolutional codes, called skew convolutional codes, that extends the class of classical fixed convolutional codes, is proposed. Skew convolutional codes can be represented as periodic time-varying convolutional codes but have a description as compact as fixed convolutional codes. Designs of generator and parity check matrices, encoders, and code trellises for skew convolutional codes and their duals are shown. For memoryless channels, one can apply Viterbi or BCJR decoding algorithms, or a dualized BCJR algorithm, to decode skew convolutional codes.

The Low Density Parity Check (LDPC) codes are linear block codes, which are Shannon Limit codes. These codes are attained least error floors of data bits for data transfer applications used in communication systems. However, the proposed LDPC codes are more beneficial than Turbo codes because of reduction in the decoding complexity and detection of the errors in less cycle time. This results the reduction of decoding time, low decoding latency and as well as least error floors in communication, when the transmitted data contains multiple error bits. This paper is proposed to represent the majority logic decoding/detecting of LDPC codes. This paper proposes the Generation of Generator and Parity Check matrices for both Binary and Non-Binary LDPC Codes. Here, the proposed Majority Logic Decoder/Detector (MLDD) is Hard decision decrypting scheme and it uses majority logic decoding based on the data transmission and reception in communication channel. This paper also elaborates the effective implementation of encoding and decoding of LDPC Codes.

Implementation of Low Density Parity Check (LDPC) decoders using conventional algorithms such as LLR BP or Min-Sum requires large amount of memory resources for storing the parity check matrix. This paper presents a soft implementation of irregular LDPC decoding for Wimax application, which achieve better BER performance and faster convergence with less memory requirement. The proposed construction reduce the memory required for loading the LDPC parity-check matrix by up to 98%, and subsequently reduce the decoding latency to 0.7 ms by iteration.

В даній роботі проаналізовано матриці перевірки на парність, які можуть бути використані в методі виправлення помилок на основі low density parity check (LDPC) матриць в системах квантового розподілу ключів. Система квантового розподілу ключів має неминучі помилки в просіяному ключі, які повинні бути виправлені алгоритмом виправлення помилок для створення захищеного ключа. У цьому аналізі 1000-бітні просіяні ключі розділяються на 50 частин, по 20 біт в кожній частині. Алгоритм створює 50 синдромів, по 10 біт в синдромі, що відповідають кожній частині, за допомогою перемноження матриць перевірки на парність розміром 10 × 20. Матриці перевірки на парність створюються алгоритмом, запропонованим Девідом Маккеєм та Редфордом Нілом. Процес створення синдрому складається з матричного перемноження 20-бітної частини просіяного ключа на матрицю перевірки на парність. Алгоритм посилає сформований синдром другій стороні. Під час передачі підслуховувач може перехопити синдром, але він не може дізнатись точне повідомлення з синдрому, навіть якщо він володіє матрицею перевірки на парність теж. Друга сторона також ділить її просіяний ключ на 50 частин, створює синдром з кожної частини і порівнює з отриманим синдромом. Якщо синдроми різні, ці частини просіяних ключів відкидають. Однак, через те, що довжина повідомлень складає 20 біт, а довжина синдромів 10 біт, можуть виникати ситуації, коли різні частини просіяного ключа матимуть однакові синдроми. Для даного випадку кожні 1024 повідомлень будуть мати один спільний синдром. Тому необхідно знайти таку оптимальну матрицю, яка знімає ймовірність отримання однакових синдромів від різних частин просіяного ключа. In this paper, the parity-check matrices that can be used in low density parity check (LDPC) based error correction method for quantum key distribution are analyzed. The quantum key distribution system has inevitable errors in sifted key that must be corrected by an error correction algorithm to create a secure key. In this analysis, 1000-bit sifted keys are divided into 50 parts. The algorithm creates 50 syndromes corresponding to each part by multiplying 10 × 20 bit parity-check matrices. The algorithm sends the generated syndrome to the other side, which also divides the sifted key into 50 parts, creates a syndrome from each part, and compares with the received syndrome. If the syndromes are different, these sifted key parts are discarded. However, there may be situations where different parts may have the same syndromes. Therefore, it is necessary to find such an optimal matrix that removes the probability of getting the same syndromes at different parts of the sifted key.

This paper proposes the use of systematic LDPC codes for hard decision Message Passing (hMP), which is a predecoder to Vector Symbol Decoding (VSD) for non-binary codes. VSD is a verification-based decoder whose outputs are decoded code words. LDPC are randomly generated and by nature, they are non-systematic codes. Using systematic instead of non-systematic codes allows the decoder to obtain the decoded data directly without a troublesome mapping step. In the simulations, 15 regular parity check matrices H are randomly generated and converted to their systematic forms. Results in a Gilbert-Elliot 2-state fading channel model with 6 different channel conditions show that hMP prefers codes with lower- weight H. For column weight of 9 bits and row weight of 18 bits, systematic H have lower weight after row operation and are better than the non-systematic ones for all channel conditions.

The communication method conveys information from the transmitter to the receiver over an intermediate medium. The competence of received information is determined by medium and clatter. There is a great need for robust error correction techniques with ever accumulative usage of wireless expedients such as portable electronic items and broadband modems. Wireless communication schemes depend on advanced error rectification techniques for their suitable functioning. Hence transferring and getting information with less or without error, while utilizing the accessible bandwidth is a foremost proposal, project necessities for present digital wireless communication systems comprising of high throughput, low power consumption, and less area. In this article, the functional analysis is performed for error control coding technique i.e., Low-Density-Parity-Check (LDPC) coding in terms of device utilization and power. The functional verification and the simulation are performed using Verilog HDL. Error correction techniques such as Linear block codes, RS codes, Convolutional codes are employed to implement forward error correction but as the constraint length increases the design of decoders becomes more complex. LDPC is a type of block code that is capable of correcting random errors. They are popular because of their eminent detection and correction capabilities. LDPC encoding technique provides high throughput and aims to improve BER when compared to conventional techniques. The decoding of LDPC codeword employs the Message Passing Algorithm, where each bit in a codeword is allocated to special nodes. The performance of these codes is hence better and easily attains Shannon’s limit than the previously used codes. Synthesis for the technique is performed and utilization reports are derived from the synthesis in Vivado.

In this chapter, we will first explain the decoding of linear block codes using syndrome tables, then provide information about some well-known preliminary binary linear block codes. Syndrome decoding is a preliminary decoding approach; most of the modern decoding techniques do not employ syndrome decoding. However, to comprehend the decoding logic of linear block codes, it is essential to understand the syndrome decoding operation. For this purpose, we first explain the construction of standard arrays and decoding operation using standard arrays. Syndromes are nothing but concise representation of standard arrays. After standard arrays, we explain the syndrome decoding concept. Following the explanation of the syndrome decoding, we introduce some linear block codes well-known in the literature, such as Golay code, Reed-Muller codes, and Hamming codes, and discuss the error correction capability and decoding operations of these linear block codes. Non-systematic forms of the generator and parity check matrices of the Hamming codes are also explained.

Entanglement-assisted quantum error-correcting codes (EAQECCs) make use of preexisting entanglement between the sender and receiver to boost the rate of transmission. It is possible to construct an EAQECC from any classical linear code, unlike standard quantum error-correcting codes, which can only be constructed from dual-containing codes. However, the number c of required ebits, which is an important basic parameter of an EAQECC, is usually calculated by computer search. In this paper, we construct four classes of MDS entanglement-assisted quantum error-correcting codes (MDS EAQECCs) based on k-Galois LCD MDS codes for some certain code lengths, where the parameter of ebits c can be easily computed algebraically and not by numerical search. Moreover, the constructed four classes of EAQECCs are also maximal-entanglement EAQECCs.

Error correction is a significant step in postprocessing of continuous-variable quantum key distribution system, which is used to make two distant legitimate parties share identical corrected keys. We propose an experiment demonstration of high speed error correction with multi-edge type low-density parity check (MET-LDPC) codes based on graphic processing unit (GPU). GPU supports to calculate the messages of MET-LDPC codes simultaneously and decode multiple codewords in parallel. We optimize the memory structure of parity check matrix and the belief propagation decoding algorithm to reduce computational complexity. Our results show that GPU-based decoding algorithm greatly improves the error correction speed. For the three typical code rate, i.e., 0.1, 0.05 and 0.02, when the block length is $10^6$ and the iteration number are 100, 150 and 200, the average error correction speed can be respectively achieved to 30.39Mbits/s (over three times faster than previous demonstrations), 21.23Mbits/s and 16.41Mbits/s with 64 codewords decoding in parallel, which supports high-speed real-time continuous-variable quantum key distribution system., 8 pages, 2 figures

This paper presents a novel linear error detection and correction approach for single and multiple bit error codes called low complexity parity check (LCPC) code. The LCPC code detects and corrects consecutive and non-consecutive bit errors. It can be used as a forward error correction scheme in the data transmission system of green wireless networks and the green Internet of Things. The proposed code improves network performance in terms of throughput, end-to-end delay, and bit error rate (BER). LCPC codes also have less complexity and lower memory requirements than Reed Solomon (RS) and low-density parity check (LDPC) codes because they have less non-zero elements in the generator matrix and the parity check matrix. Unlike LDPC codes, LCPC codes do not require reiteration in the decoding process. Various code rates of the LCPC code are proposed to reduce the complexity of the encoding and decoding process, which in turn decreases energy consumption. Simulation results show that the proposed LCPC (9, 4) code outperforms the popular LDPC codes. Compared with the LDPC (8, 4) with the decode bit flip algorithm, LCPC (9, 4) offers a coding gain of nearly 3 dB at a BER equal to 10−5.

Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings, have raised significant concerns in its real applications. Recent studies even show that the common memory error repair “remedies” cannot efficiently address them. In this article, we for the first time systematically study the potentials of the strong low-density parity-check (LDPC) code for combating such unique asymmetric errors in both single-level-cell (SLC) and multi-level-cell (MLC) STT-RAM designs. A generic STT-RAM channel model suitable for the SLC/MLC designs, is developed to analytically calibrate all the accumulated asymmetric factors of the write/read operations. The key initial information for LDPC decoding, namely asymmetric log-likelihood ratio (A-LLR), is redesigned and extracted from the proposed channel model, to unleash the LDPC’s asymmetric error correcting capability. LDPC codec is also carefully designed to lower the hardware cost by leveraging the systematic-structured parity check matrix. Then two customized short-length LDPC codes—(585,512) and (683,512)—augmented from the semi-random parity check matrix and the A-LLR based asymmetric decoding, are proposed for SLC and MLC STT-RAM designs, respectively. Experiments show that our proposed LDPC designs can improve the STT-RAM reliability by at least 10 2 (10 4 ) when compared to the existing error correction codes (ECCs) for the SLC (MLC) design, demonstrating the feasibility of LDPC solutions on STT-RAM.

In this paper, we propose a generalized minimum-sum decoding algorithm using a linear approximation (LAMS) for protograph-based low-density parity-check (PB-LDPC) codes with quasi-cyclic (QC) structures. The linear approximation introduces some factors in each decoding iteration, which linearly adjust the check node updating and channel output. These factors are optimized iteratively using machine learning, where the optimization can be efficiently solved by a small and shallow neural network with training data produced by the LAMS decoder. The neural network is built according to the parity check matrix of a PB-LDPC code with a QC structure which can greatly reduce the size of the neural network. Since, we optimize the factors once per decoding iteration, the optimization is not limited by the number of the iterations. Then, we give the optimized results of the factors in the LAMS decoder and perform decoding simulations for PB-LDPC codes in fifth generation mobile networks (5G). In the simulations, the LAMS algorithm shows noticeable improvement over the normalized and the offset minimum-sum algorithms and even better performance than the belief propagation algorithm in some high signal-to-noise ratio regions.

In this paper, we design an irregular low-density parity-check (LDPC) codes for unequal inter-symbol interference channels based on the modified extrinsic information transfer chart. During transmission, each LDPC codeword will be divided and transmitted to the different channels. The aim of this scheme is to avoid transmitting the whole codeword in a high error rate channel. The simulation results show that the proposed code optimized for both PR1 and PR2 channels can achieve a 0.2 coding gain over the codes designed specifically for each individual channel. When this simple code is applied to a perpendicular channel with these two targets, the coding gains of the proposed code is about 0.08 dB at the frame error rate of $10^{-3}$ .

In this paper, we discuss the belief propagation (BP) decoding of polar codes. The performance of polar codes for short lengths is not satisfactory. Therefore, motivated by this we propose a novel technique to improve the performance of polar codes under BP decoding. In order to enhance the reliability of the variable nodes’ propagated messages in BP decoding, the messages are multiplied by previous messages of variable nodes. It is also shown that the BP decoding can be performed on polar codes if the factor graph is constructed according to the parity check matrix of polar codes. Simulation results in binary-input additive white Gaussian noise channel show that using the proposed method a gain of 1–2 dB can be achieved. We also show that the complexity of proposed decoder is same as the complexity of standard BP decoder. Furthermore, we show that the proposed decoder requires about 10–25 iterations less than the standard BP decoder.

The LDPC codes are Shannon Limit codes that can achieve low bit error rates for SNR applications. The features of LDPC Codes are reduction in the decoding time, latency and as well as no error-floors at high SNRs. The proposed algorithms are SBF, MSA, and MLDD. The various decoding algorithms have been compared for these codes. The parameters are describing the which algorithm further helps in selecting the better decoder used for Medical and Signal Processing Applications. These codes are also used in Generating the Barcodes depends on the size of the Parity Check matrix.

For correcting burst errors in channels with memory are widely used various code constructions together with interleaving. For increasing the reliability of information transmission in such channels is advisable to apply algebraic interleaved convolutional codes. The principles of polynomial and matrix representation of algebraic interleaved convolutional codes with predetermined coding rate are given. The parameters of these codes which completely determined by the modified generator polynomial are presented. Algebraic decoding these codes has been a large computational complexity and limited correction capability. Algebraic interleaved convolutional codes can be represented as a long binary block codes which can be determined with using generator or parity check matrix. The combination approach to iterative decoding these codes whose purpose is to find the most probable codeword by assessing a log likelihood ratio of each code symbol is proposed. The share using information about the reliability of symbols, adaptive belief propagation and natural computing procedures are offered. According to this approach each iteration of decoding starts with finding the expected codeword using natural computing procedures. If the received vector is not codeword, then adaptive belief propagation procedures are used for updating the information about the reliability of symbols which then used in the next iteration of decoding. The basic principles of implementation of the main steps of the proposed method decoding algebraic interleaving convolution codes are presented.

Recent developments in the field of deep learning have motivated many researchers to apply these methods to problems in quantum information. Torlai and Melko first proposed a decoder for surface codes based on neural networks. Since then, many other researchers have applied neural networks to study a variety of problems in the context of decoding. An important development in this regard was due to Varsamopoulos et al. who proposed a two-step decoder using neural networks. Subsequent work of Maskara et al. used the same concept for decoding for various noise models. We propose a similar two-step neural decoder using inverse parity-check matrix for topological color codes. We show that it outperforms the state-of-the-art performance of non-neural decoders for independent Pauli errors noise model on a 2D hexagonal color code. Our final decoder is independent of the noise model and achieves a threshold of $10 \%$. Our result is comparable to the recent work on neural decoder for quantum error correction by Maskara et al.. It appears that our decoder has significant advantages with respect to training cost and complexity of the network for higher lengths when compared to that of Maskara et al.. Our proposed method can also be extended to arbitrary dimension and other stabilizer codes., Comment: 12 pages, 12 figures, 2 tables, submitted to the 2019 IEEE International Symposium on Information Theory

LDPC is being enormously used these days in number of communication applications for its reliably and resourcefulness over a certain channel. LDPC decoding “Sum-Product Algorithm and Minimum Sum Algorithm” are implemented and compared in this paper. The parity check matrix used is unique in its construction; sparse method is used to generate the matrix. The decoder is simulated in MATLAB. Performance and effectiveness of algorithms is verified under the presence of noise.

As a recently proposed physical layer security scheme, the two-dimensional transmission scheme prevents eavesdropping, but the bit error rate (BER) of the receiver becomes high. A new coding scheme for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes to improve the performance of the receiver is proposed and named as dimension reduction coding. This new scheme constructs the base matrix, which is necessary to obtain the parity check matrix of QC-LDPC codes, from the channel coefficient matrix of two-dimensional transmission scheme. Then, by analyzing the relationship between the base matrix and the parity check matrix of QC-LDPC codes, we find out the conditions that the base matrix must satisfy so that the corresponding parity check matrix has no shortest cycle in Tanner graph. Furthermore, a dimension reduction algorithm is presented to modify the base matrix and obtain parity check matrices with good performance. Finally, simulation results are given and validate the feasibility of this method.

This paper presents a novel efficient encoding method and a high-throughput low-complexity encoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes for the 5th-generation (5G) New Radio (NR) standard. By storing the quantized value of the permutation information for each submatrix instead of the whole parity check matrix, the required memory storage size is considerably reduced. In addition, sharing techniques are employed to reduce the hardware complexity. The encoding complexity of the proposed method was analyzed, and indicated a substantial reduction in the required area as well as memory storage when compared with existing state-of-the-art encoding approaches. The proposed method requires only 61% gate area, and 11% ROM storage when compared with a similar LDPC encoder using the Richardson&ndash, Urbanke method. Synthesis results on TSMC 65-nm complementary metal-oxide semiconductor (CMOS) technology with different submatrix sizes were carried out, which confirmed that the design methodology is flexible and can be adapted for multiple submatrix sizes. For all the considered submatrix sizes, the throughput ranged from 22.1&ndash, 202.4 Gbps, which sufficiently meets the throughput requirement for the 5G NR standard.

In large scale distributed systems such as cloud storage systems, erasure coding is a fundamental technique to provide high reliability at low monetary cost. Compared with the traditional disk arrays, cloud storage systems use an erasure coding scheme with both flexible fault tolerance and high scalability. Thus, Reed-Solomon (RS) Codes or RS-based codes are popular choices for cloud storage systems. However, the decoding performance for RS-based codes is not as good as XOR-based codes, which are optimized via investigating the relationships among different parity chains or reducing the computational complexity of matrix multiplications. Therefore, exploring an efficient decoding method is highly desired. To address the above problem, in this paper, we propose an Advanced Parity-Check Matrix (APCM) based approach, which is extended from the original Parity-Check Matrix based (PCM) approach. Instead of improving the decoding performance of XOR-based codes in PCM, APCM focuses on optimizing the decoding efficiency for RS-based codes. Furthermore, APCM avoids the matrix inversion computations and reduces the computational complexity of the decoding process. To demonstrate the effectiveness of the APCM, we conduct intensive experiments by using both RS-based and XOR-based codes under cloud storage environment. The results show that, compared to typical decoding methods, APCM improves the decoding speed by up to 32.31% in the Alibaba cloud storage system.

Non-binary low-density parity-check (NB-LDPC) codes exhibit a much better performance than their binary counterparts, especially for moderate codeword length and high-order modulation. However, their decoding algorithms suffer from very high computational complexity. In this paper, a low-complexity algorithm is proposed, named parity-check erased algorithm (PCEA), where an additional parity check bit is added to each symbol of the codeword when encoding and a series of simple operations are performed based on these bits during decoding. As a universal joint coding and decoding algorithm, the PCEA can be combined with arbitrary NB-LDPC encoding schemes and decoding algorithms based on message passing. The proposed algorithm facilitates significant improvement of decoding performance with a small decrease of the code rate. Additionally, it usually has an even better performance than a nearly same-rate code constructed by the original method, and requires much lower decoding complexity due to smaller size of the parity check matrix.

This paper presents hardware-friendly LDPC decoding schedules for 5G hybrid automatic repeat request (HARQ) applications. Since there are built-in punctured blocks in the parity check matrix (PCM), a scheduling technique is proposed that allows the punctured nodes to be efficiently recovered. For HARQ using the Chase combining (CC), the previous decoding results corresponding to the punctured part are retained, and the proposed layered decoding is arranged according to the row weight. For HARQ using the incremental redundancy (IR) approach, the parity bits corresponding to the pure-row-orthogonal part of the PCM are transmitted first. The hardware implementation shows that the throughput can be increased by 21.37% for the first decoding attempt, 56.9% for CC-HARQ and 14.51% for IR-HARQ when the code rate reaches 0.303.

This paper presents a novel method for constructing high performance unequal error protection (UEP) quasicyclic low-density parity-check (QC-LDPC) codes. These codes are highly efficient and designed with flexible rates, lengths and number of protection levels. The given QC-LDPC codes are based on the combinatorial design. Each circulant constituting the parity check matrix of the UEP code is determined from subsets with the distinct difference between elements. Simulation results indicate that proposed UEP codes have equivalent performance to UEP codes constructed with the higher girth and lower rate, while achieving superior performance than the codes constructed by conventional equal error protection (EEP) techniques.

This paper presents a new construction of error correcting codes which achieves optimal recovery of a streaming source over a packet erasure channel. The channel model considered is the sliding window erasure model, with burst and arbitrary losses, introduced by Badr et al. . Recently, two independents works by Fong et al. and Krishnan and Kumar have identified optimal streaming codes within this framework. In this paper, we introduce streaming code when the rate of the code is at least 1/2. Our proposed construction is explicit and systematic, uses off-the-shelf maximum distance separable (MDS) codes and maximum rank distance (MRD) Gabidulin block codes as constituent codes and achieves the optimal error correction. It presents a natural generalization to the construction of Martinian and Sundberg to tolerate an arbitrary number of sparse erasures. The field size requirement which depends on the constituent MDS and MRD codes is also analyzed., Comment: 22 pages

Low density parity check (LDPC) codes are forward error-correction codes, invented by Robert Gallager in his MIT Ph.D. dissertation, 1960. The LDPC codes are ignored for long time due to their high computational complexity and domination of highly structured algebraic block and convolutional codes for forward error correction. A number of researchers produced new irregular LDPC codes which are known as new generalizations of Gallager’s LDPC codes that outperform the best turbo codes with certain practical advantages. LDPC codes have already been adopted in satellite-based digital video broadcasting and long-haul optical communication standards. This chapter discusses LDPC code properties, construction of parity check matrix for regular and irregular LDPC codes, efficient encoding and decoding of LDPC codes, and performance analysis of LDPC codes.

To partially compensate the inefficiency of random codes, we can use Reed–Solomon codes, these codes can be decoded from a block with the maximum possible number of erasures in time quadratic in the dimension. But in practice, these algorithms are often too complicated and quadratic running times are still too large for many applications. Hence, a new class of codes is needed to construct robust and reliable transmission schemes and such a class of codes is known as fountain codes.

Iterative algorithms based on belief propagation can perform very close to optimal ML decoding for long LDPC codes. However, for short LDPC codes over Binary Erasure Channels (BEC) their performance drops significantly. In this paper, we introduce an iterative LDPC decoder over BEC by using our novel deep recurrent neural logic networks that learns Boolean logic algebra. It turned out that the neural logic network is capable of learning discrete algorithmic tasks and suitable for decoding LDPC codes. We show that the proposed decoding method can outperform the belief propagation algorithm for short LDPC code while using significantly fewer number of iterations. We further demonstrate that the proposed model is able to generalize very well. In other words, the model that was trained for specific settings such as channel erasure, parity check matrix, and code length, when tested under various other settings, still performed almost as if it was trained for those new settings.

At present, steganography has a wide range of problems such that the user has lower participation in the steganography process and it's difficult to ensure the security of the steganography algorithm. This is the main cause that steganography cannot go out of laboratory to become practical. In order to solve this problem, this paper proposed a multi-modal adaptive steganography algorithm with variable parity check matrix. Based on the guarantee of high anti-statistical detection, the algorithm gets multiple embedding modification modes by controlling the parity check matrix structure using shared key and establishing the mapping relationship between the key and the height, width of the parity check matrix. Thus, the steganography algorithm becomes secure and controllable for users. The security analysis and experimental results show that the algorithm has higher complexity and can maintain high anti-statistical detection.