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A 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed and investigated for the first time. The device features dual deep-oxide trenches (DDOTs) formed in the drift region. TheDDOT assists in sustaining the electric potential from the collector, which enables the SOI-LIGBT to reduce its drift region length. At the same breakdown voltage of 560 V, the drift region length is reduced from 47~\mu \textm for the conventional SOI-LIGBT to 23.4~\mu \textm for the proposed SOI-LIGBT. Due to the small-sized drift region, decreased amount of stored carrier and fast depletion of the drift region during the turn-off process are realized. The experiments demonstrate that the proposed SOI-LIGBT exhibits a superior tradeoff between turn-off loss ( E \mathrm{\scriptscriptstyle OFF}) and on-state voltage drop ( V \mathrm{\scriptscriptstyle ON}) to the conventional SOI-LIGBT. E \mathrm{\scriptscriptstyle OFF} of the proposed DDOT SOI-LIGBT is 36.9% lower than that of the conventional SOI-LIGBT at the same V \mathrm{\scriptscriptstyle ON} of 1.61 V. The DDOT can be fabricated simultaneouslywith the formation of the isolation trenches in a developed SOI bipolar–CMOS–DMOS–IGBT process. [ABSTRACT FROM PUBLISHER]

This paper proposes a U-shaped channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual trenches to reduce the turn-off loss while keep the low ON-state voltage drop. The device features a U-shaped gate trench (G1) and a U-shaped hole-barrier trench (G2). By introducing the dual trenches, enhanced carrier stored effect at the emitter side, more uniform carrier distribution in the drift region, and low carrier density at the collector are realized, resulting in decreases of ON-state voltage drop ( V\mathrm{\scriptscriptstyle ON} ) and turn-OFF loss ( E\mathrm{\scriptscriptstyle OFF}) . The proposed SOI-LIGBT offers an E\mathrm{\scriptscriptstyle OFF}~52.3 % lower than the conventional planar-gate U-shaped channel SOI-LIGBT at the same V\mathrm{\scriptscriptstyle ON} of 1.22 V. Moreover, the proposed SOI-LIGBT exhibits a latch-up free characteristic at the current density larger than 1200 A/cm2. [ABSTRACT FROM AUTHOR]

A novel 500 V reverse-conducting (RC) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual embedded diodes (DEDs) is proposed to eliminate the snapback, and its mechanism is investigated by simulation. The RC is realized by the internal diode, which consists of two p-i-n diodes (D1 and D2). The two diodes are connected in series. In the RC-state, the current flows through D1 first and then through D2. D2 is embedded in the anode region of the proposed DED-LIGBT and is fully isolated by the deep-oxide trench. In the forward conducting state, D2 is reverse biased and the electrons from the N+ cathode can only flow into the P+ anode. The DEDs reroute the electron current path, and thus, the snapback is avoided. Moreover, by adjusting the width of D2 ( Wb) , the internal diode of the DED structure achieves superior reverse recovery time ( t\text {rr}) and reverse recovery peak current ( I\text {rrm}) to the conventional SOI p-i-n diode. [ABSTRACT FROM AUTHOR]