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In a high-power semiconductor power module where multiple chips are populated in parallel, the thermal imbalance problem arises. In this article, the next-generation standard high-voltage insulated-gate bipolar transistor module for high-speed railcar traction is investigated to characterize the internal thermal imbalance among paralleling chips and evaluate the impact on temperature distribution in field application. The former is accomplished by a new test algorithm with a purposely designed module sample, while the latter is achieved via an advanced electro-thermal simulation from chip level to system level. The experimentally verified thermal network among paralleling chips reveals the multiple reasons for the thermal imbalance. A comparison between the simulation and experimental results regarding the paralleling chips’ power-cycling scenario helps to confirm the effectiveness of the chip model, the thermal network, and the electro-thermal simulation approach. A further electro-thermal simulation shows that the module internal thermal imbalance can lead to significant junction temperature discrepancy among paralleling chips in traction inverter applications, which should be taken into consideration for the long-term reliability assessment. [ABSTRACT FROM AUTHOR]

A method to derive the junction-to-case level coupling thermal resistances among paralleling chips in the multichip semiconductor power module has been proposed in this article. It is revealed that the traditional structure function methodology (SFM), which is developed for analyzing the self-heating effect of the driving-point chip, cannot be applied directly in the thermal coupling analysis, where the influence of the driving-point chip on the neighboring acceptor chip is concerned. This article shows that by combining the traditional SFM with the frequency-domain analysis (FDA), the effective separation points between the module case and the external cooling setup can be identified in both time and frequency domains, which correspond to the characteristic frequency points in the complex loci of the thermal impedance curves. By extracting the amplitudes at the characteristic frequencies from the complex loci in the FDA, the junction-to-case level coupling thermal resistances can be derived. Both simulation and experimental study have been carried out to verify the concept. The agreement between the two justifies the proposed method. [ABSTRACT FROM AUTHOR]

We present in this paper an advanced electromagnetic (EM)-electrothermal analysis approach for the semiconductor power devices, with illustration on the insulated-gate bipolar transistor (IGBT) modules. This method distinguishes itself by dynamically integrating the EM domain into the circuit-type electrothermal coupling analysis, thus enabling the multi-dimensional simulation that spans in time from nanoseconds to seconds, and in space from chip level to system level. In particular, it contains a parametric-extracted electrothermal model of the IGBT chip and a comprehensive 0-D thermal network as well as an EM network extracted from the 3-D module packaging structure for each paralleling chip. The incorporation of the EM, as well as thermal networks representing the 3-D packaging structure, reveals essential information about the current imbalance, power dissipation imbalance, and thermal imbalance inside the IGBT module with paralleling chips, which have a strong influence on the module reliability. To demonstrate the application of this approach, an unfavorably designed 1700-V/450-A half-bridge IGBT power module is evaluated in the simulation circuit, with experimentally verified electrothermal IGBT chip model and thermal as well as EM networks. The results have shown that the EM-electrothermal analysis can successfully reveal the dynamic interaction among different physical domains and, thus, the current as well as temperature imbalance among the paralleling chips inside the power module. The predicted current imbalance also agrees with that from the experimental test. [ABSTRACT FROM AUTHOR]